A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources


This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype.



  1. Hybrid multilevel inverter
  2. DC-link inverter
  3. Half-bridge module
  4. Symmetric DC voltage supply




Fig. 1. The proposed three-phase CMLI with two half-bridge cells per phase leg 



Fig. 2. Simulation results of the output line voltages and line currents for (a) load of nearly 0.8–lagging power factor and (b) load of nearly unity power factor

Fig. 3. Simulation results for a dynamic change in the load from nearly unity PF (100.31∠4.49°Ω) to 0.8 lagging PF (127.13∠38.13°Ω): (a) level generator output voltage, (b) polarity generator output voltage (phase voltage) and (c) line voltage and line current

Fig. 4 Simulation results for a dynamic change in the load from nearly 0.9 lagging PF (108.01∠22.21°Ω) to 0.7 lagging PF (142.88∠45.58°Ω): (a) level generator output voltage, (b) polarity generator output voltage (phase voltage) and (c) line voltage and line current

Fig. 5 Simulation results for a dynamic change in the load magnitude with the same PF: (a) Line voltage, (b) Line current

Fig. 6 Simulation results for carrier frequency of 8 kHz: (a) line voltages and currents, (b) line current THD, (c) line voltage THD



This paper presents a new symmetrical multilevel inverter topology with two different stages. The proposed inverter requires less power electronic devices and features modularity, hence simple structure, less cost, and high scalability. The number of input DC-supplies for the proposed topology is found to be nearly 67% less than the similar symmetric half-bridge topologies, which is a great achievement for industrial applications. This phenomenon will reduce the complexity of DC voltage management. As being a symmetric structure, all the switching devices experience same voltage stress, which is a very important factor for high voltage applications. The feasibility of the proposed inverter is confirmed through simulation and experimental analysis for different operating conditions.



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