A Common Capacitor Based Three Level STATCOM and Design of DFIG Converter for a Zero-Voltage Fault Ride-Through Capability

ABSTRACT:

To meet the augmented load power demand, the doubly-fed induction generator (DFIG) based wind electrical power conversion system (WECS) is a better alternative. Further, to enhance the power flow capability and raise security margin in the power system, the STATCOM type FACTS devices can be adopted as an external reactive power source. In this paper, a three-level STATCOM coordinates the system with its dc terminal voltage is connected to the common back-to-back converters. Hence, a lookup table-based control scheme in the outer control loops is adopted in the Rotor Side Converter (RSC) and the grid side converter (GSC) of DFIG to improve power flow transfer and better dynamic as well as transient stability. Moreover, the DC capacitor bank of the STATCOM and DFIG converters connected to a common dc point. The main objectives of the work are to improve voltage mitigation, operation of DFIG during symmetrical and asymmetrical faults, and limit surge currents. The DFIG parameters like winding currents, torque, rotor speed are examined at 50%, 80% and 100% comparing with earlier works. Further, we studied the DFIG system performance at 30%, 60%, and 80% symmetrical voltage dip. Zero-voltage fault ride through is investigated with proposed technique under symmetrical and asymmetrical LG fault for super-synchronous (1.2 p.u.) speed and sub-synchronous (0.8 p.u.) rotor speed. Finally, the DFIG system performance is studied with different phases to ground faults with and without a three-level STATCOM.

KEYWORDS:

  1. Doubly-fed induction generator (DFIG)
  2. Field oriented control (FOC)
  3. Common-capacitor based STATCOM
  4. Voltage compensation
  5. Balanced and unbalanced faults
  6. Zero-voltage fault ride through

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Figure 1. Grid-Connected DFIG With Three Levels Statcom Converter.

EXPECTED SIMULATION RESULTS:

Figure 2. DFIG Operation With 50% Voltage Dip (I) Using Method In [27]. And (Ii) Using Proposed Method.

Figure 3. DFIG Operation With 50% Voltage Dip (I) Using Method In [28] And (Ii) Using Proposed Method.

Figure 4. DFIG Operation With (I) 30% Dip, (Ii) 60% Dip And (Iii) 80% Dip In Grid Voltage.

Figure 5. Rotor, Stator Gsc And Grid Terminal Current Waveforms With The Proposed Technique With Slg Fault.

CONCLUSION:

A generalized DFIG wind energy conversion system based test-bed system connected to the grid is considered in the paper. The work tested in the starting cases with two different research papers works with proposed method under an 80% dip. Later, proposed methodology compared under 30%, 60%, and 80% dip, and the DFIG behavior is examined. Further, under three different cases, LG, LLG and LLG faults without and STATCOM are compared to show STATCOM controller’s effectiveness. An improved field-oriented control scheme for the DFIG with real and reactive power lookup-based control in the outer control loops. It is observed that, there is a rapid development in the back emf and decoupled current regime in the paper’s inner control loops is proposed. A three-level SATCOM is used in this paper, with the rectifier end dc-link connected to the common capacitor between the DFIG back-to-back converters. A better damping factor is observed for torque, powers, current, voltage, and speed at 60%, 80%, and 100% dip with the proposed scheme.

The proposed method employs the adjustment of external real and reactive powers using the optimal lookup table method as shown in Table 3, rotor speed, and terminal voltage in the outer control loops of both RSC and GSC. The inner control loop is fast-acting current control and back emf- based voltage injection near the decoupling voltage loop. The strategy works on decoupled real and reactive power flow controls in synchronous rotating frames leads to individual power control. This technique improves performance under normal conditions and during grid faults, with better rotor voltage control, rotor speed, and damping. The post-fault behavior of an overall system improved using the proposed technique.

Further improvement in the system behavior is observed with the common- dc link STATCOM. The rectifier end dc link is connected to the capacitor between the DFIG converters, which will reduce the cost for capacitor and measurement sensors. This paper demonstrates the DFIG-based WECS with better active and reactive power and EMT damping, surge current reduction, speed control, and effective LVRT capability. There are distortions in the rotor current waveform during the zero-voltage fault ride during the fault and considerably more when the rotor speed is at super synchronous speed. When the rotor speed is beyond the synchronous speed, the rotor current is injected into the stator terminal from the rotor side windings with RSC control scheme. Under this condition, the fault inrush current from the dc-link capacitor will pass through this rotor terminal and reach the stator windings. Under sub-synchronous speed, the rotor winding will receive the current for the stator windings, so the fault effect is less influenced at lower speeds than with higher speeds. The rotor voltage is maintained at both speeds during the LG fault. However, waveform is less distorted with lower rotor speed.

The dc-link voltage distortions during the fault are more with super- synchronous speed than sub-synchronous speed operation for zero voltage ride through. The dc-link voltage is more stubborn and stable when the rotor speed is lesser than the synchronous speed. The STATCOM current is observed to be more in faulty phase than with other two healthy phases. The reason and analysis are the same as that with the symmetrical fault study. The deviation of the fault current at the STATCOM terminal is re-injected to the grid via the closed path with the dc-link capacitor terminal. The post-fault performance is superior with a serious 100% voltage dip case and also found better dynamic response because of the RSC and GSC proposed technique and the STATCOM controller. Further, an effective operation is experienced with a common link dc capacitor STATCOM than with a conventional topology. Hence, simulated results show better performance and profitable operation during and after the faults than the earlier famous methods.

With the proposed method, rotor and stator current during fault are maintained, not getting zero value and limiting surge currents to a dangerous value. However, stator and rotor current is not supported to their pre-fault value during the fault period. The torque reduction to a smaller value observed increases the grid fault dip value, but there are no surges and oscillations with the proposed method. The rotor speed is also maintained almost constant even for significant voltage dip. As a result, the post fault recovery in the DFIG is smooth and instantaneous, observed for winding voltages, currents, EMT, active and reactive powers, dc-link capacitor voltage, and rotor speed.

All the objectives specified in the Introduction section are met 1) rotor and stator current surges are limited, current surges ate within 1.5 times the operating value, mitigation in the rotor voltage observed. Furthermore, the reactive power support by STATCOM, RSC and GSC improved the DFIG WECS during and after the fault. Thereby 1) enhancement in overall dynamic and transient stability is observed. 2) The rotor speed is almost constant even for a significant grid voltage dip which is better than many research papers. 3) The electromagnetic torque (EMT) and active and reactive power flow oscillations are damped completely, and sustainable control observed with the technique. 4) The proposed method is suitable for grid faults like symmetrical, asymmetrical, and recurring faults. Better DFIG performance is expected with LVRT capability for symmetrical and asymmetrical faults with future research activities.

REFERENCES:

[1] H. A. Mohammadpour, A. Ghaderi, H. Mohammadpour, and E. Santi, “SSR damping in wind farms using observed-state feedback control of DFIG converters,” Electr. Power Syst. Res., vol. 123, pp. 57_66, Jun. 2015.

[2] F. Blaabjerg and K. Ma, “Future on power electronics for wind turbine systems,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 1, no. 3, pp. 139_152, Sep. 2013.

[3] T. D. Vrionis, X. I. Koutiva, and N. A. Vovos, “A genetic algorithm based low voltage ride-through control strategy for grid connected doubly fed induction wind generators,” IEEE Trans. Power Syst., vol. 29, no. 3, pp. 1325_1334, May 2014.

[4] A. M. Eltamaly and H. M. Farh, “Maximum power extraction from wind energy system based on fuzzy logic control,” Electr. Power Syst. Res., vol. 97, pp. 144_150, Apr. 2013.

[5] Y. Weng and Y. Hsu, “Sliding mode regulator for maximum power tracking and copper loss minimisation of a doubly fed induction generator,” IET Renew. Power Gener., vol. 9, no. 4, pp. 297_305, May 2015.

Modeling and Simulation of Impedance Distance Relay for Fault Location and Protection of Single Wire Earth Return Line

ABSTRACT:

Different technologies and resources are utilized to provide electricity access for the rural population around the world. Single wire earth return (SWER) line gets prominent attention around the globe to electrify low load profile customers and remote load like telecom base stations by extending from the nearby medium grid. SWER distribution system is designed by tapping from medium voltage distribution line using an isolation transformer. Unlike other distribution systems, the secondary side of a transformer has an only single line with dedicated perfect grounding system. SWER lines are considered as a cost-effective solution, compared to the three phase grid extension by electric utility companies. Since line route is mostly in rural areas with different geographical topologies, natural and human-made faults are inevitable scenarios on the line. According to a preference of utilities and geographical locations, SWER lines are equipped with over current relay, surge arrestors or reclosers to isolate faulty line during the fault. The two main challenges on SWER line protection are to back up existing over current protection relay when it fails to clear the fault and to locate the location of fault for line maintenance. Technicians patrol up to hundreds of km along SWER line to locate a fault. This activity will be inefficient and time-consuming way of locating the fault. In this paper, we model and simulate the impedance distance relay to back up existing protection system and locate the fault. Our model successfully backs up definite time over current (DTOC) relay for a single line to ground (SLG) faults across the line. Consequently, fault locator-block locates the faulty line position.

KEYWORDS:

  1. SWER
  2. Rural Electrification
  3. Impedance relay
  4. Fault location
  5. Protection

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig.1.Impedance relay simulation model

EXPECTED SIMULATION RESULTS:

Fig.2.Fault cleared by DTOC

Fig.3.Fault cleared by Zone-1 relay

Fig.4.Fault cleared by zone -2 relay

CONCLUSION:

In this paper, the two challenges on SWER line, backup protection of DTOC relay and fault location during fault are addressed. An impedance relay is proposed to backup DTOC relay and to locate faults on SWER line.The simulation is done on MATLAB/SIMULINK on each step of 15km from relay point to the entire line. A fault is simulated at 0.4 s and during the inception of fault, the proposed impedance relay managed to clear the fault according to the intentional time delay set between each zone when DTOC fails to operate. Fault locator-block also measures the fault location by considering fault impedance during a fault. The model can measure a SWER line fault location for a fault impendence of 5Ω and below with less than 3% errors. Whereas, fault impedance compensation is required for a fault impedance greater than 10Ω to achieve better result with minimum error percentage.

REFERENCES:

[1] P. Cook, “Infrastructure, rural electrification and development,” Energy Sustinable Development , pp. 304-313, 2011.

[2] IEA, “Iea.org/sdg/electricity/,” IEA, [Online]. Available: https://www.iea.org/sdg/electricity/. [Accessed 10 03 2019].

[3] ESAMP, “Reducing the Cost of Grid Extension for Rural Electrifcation,” The International Bank for Reconstruction and Development 227.200, USA, 2000.

[4] L.MANDENO, “RURAL POWER SUPPLY, ESPECIALLY IN BACK COUNTRY AREAS.,” in Proceedings of the New Zealand Institution of Engineers, Vol. 33 (1947), 1947.

[5] P. Grad, “Energy Source & Distribution,” 2014, 18 May 2014. Available: https://www.esdnews.com.au/swer-still-going-strong/. [Online] [Accessed 11 March 2019].

Transmission Line Protection with Distance Relay

ABSTRACT:

 With the development in science and engineering the power system protection field also get advanced which includes the development of relays .the relays journey started by electromechanical then solid state and now digital and numerical relays .An economical and feasible solution to investigate the performance of relays and protection system offered by modeling of protective relays .Distance relay is one of the effective protective relays that are used for the protection of extra high voltage transmission lines. Distance relays are considered of the high speed class and can provide protection. To detect the fault on transmission lines many distance relays are used but for long transmission line mho relay is most suited. The proposed work is about designing of numerical mho relay in MATLAB / SIMULINK to be used for distance protection schemes of long distance transmission lines with better result and characteristics. The required mho relay algorithm is evaluated by using MATLAB to model the power system under different fault condition and simulate it by using phasor based method available in MATLAB simulation. Thus the modeling and simulation of numerical mho relay gives the improved result and greatly enhance the performance of mho relay

KEYWORDS:

  1. Distance protection
  2. Numerical relays
  3. Matlab/Simulink

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

EXPECTED  SIMULATION RESULTS:

CONCLUSION:

This work presents a detailed phasor model for a distance relay of mho characteristics. Mho relays are inherently directional so there is no need for directional elements in the relay model. Here the developed simulation is evaluated for line to line fault on the system, and the results found as Simulation results of different faults regarding type and position show clearly the accurate performance of the developed distance relay model. From results it is seen that speed of operation of numerical mho relay is faster than impedance relay. The model versatility, adaptability and applicability promote it for use in power system simulators. Also, it can be used as a training tool to help users understand how a distance relay works and how settings are performed.

REFERENCES:

I. P.G. Mclaren SM, G.W. Swift SM, 2. Zhang, E. Dirks, R.P. Jayasinghe, I. Fernandouniversity Of Manitoba, Winnipeg, Manitoba, Canada, R3T 2N2.” A New Directional Element For Numerical Distance Relays” IEEE Transactions On Power Delivery, Vol. 10, No. 2, April 1995.

II. P. G. Mclaren, K. Mustaphi, G. Benmouyal, S. Chano, A. Girgis, C. Henville, M. Kezunovic, L. Kojovic, R. Marttila, M. Meisinger, G. Michel, M. S. Sachdev, V. Skendzic, T. S. Sidhu, And D. Tziouvaras” Software Models For Relays” IEEE Transactions On  Power Delivery, VOL. 16, NO. 2, APRIL 2001.

III. Shailendra Kumar Saroj, Harish Balaga, D. N. Viswakarma (Banaras Hindu University), Varanasi, India ” Discrete Wavelet Transform Based Numerical Protection Of Transmission Line ”, Department Of Electrical Engineering Indian Institute Of Technology

IV. Li-Cheng Wu, Chih-Wen Liu, Ching-Shan Chen,Member, National Taiwan University, Taipei, Taiwa, “Modeling And Testing Ofa Digital Distance Relay Using MATLAB / SIMULINK ,IEEE Transaction On Power Delivery,2005.

V. Eng. Abdlmnam A. Abdlrahem , Dr.Hamid H Sherwali Modelling Of Numerical Distance Relays Using Matlab ”, “IEEE Symposium On Industrial Electronics And Applications”,Octobe,2009.

Implementation and Evaluation a SIMULINK Model of a Distance Relay in MATLAB/SIMULINK

ABSTRACT:

This paper describes the opportunity of implementing a model of a Mho type distance relay with a three zones by using MATLAB/SIMULINK package. SimPowerSystem toolbox was used for detailed modeling of distance relay, transmission line and fault simulation. The proposed model was verified under different tests, such as fault detection which includes single line to ground (SLG) fault, double line fault (LL), double line to ground fault (LLG) and three phase fault, all types of faults were applied at different locations to test this model. Also the Mho R- jX plain was created inside this model to show the trajectory of measured apparent impedance by the relay. The results show that the relay operates correctly under different locations for each fault type. The difficulties in understanding distance relay can be cleared by using MATLAB/SIMULINK software.

KEYWORDS:

  1. Power system protection
  2. Distance relay
  3. Line protection
  4. MATLAB/SIMULINK
  5. Apparent Impedance

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Figure 1. Overall simulation model

CONCLUSION:

A Mho type distance relay was successfully developed based on MATLAB/SIMULINK package, (each part of the relay is implemented as a separate function). Each function has been created using special blocks of SIMULINK. By testing the behavior of the developed relay model under different fault conditions, the relay model was able to recognize the appropriate fault type. From perspective impedance calculations, the relay model has the ability of indicating the correct zone of operation in all cases. The relay identifiers the fault locations as expected, as the fault location is changed, the measured impedance change consequently. The impedance path which reflects the behavior of the model under different fault conditions was presented and discussed

REFERENCES:

[1] Anderson. P.M.”Power System Protection”, ISBN 0-07-134323-7 McGraw-Hill,1999.

[2] Muhd Hafizi Idris, Mohd Saufi Ahmad, Ahmad Zaidi Abdullah, Surya Hardi “Adaptive Mho Type Distance Relaying Scheme with Fault Resistance Compensation” 2013 IEEE 7th International Power Engineering and Optimization Conference (PEOCO2013), Langkawi, June 2013.

[3] M. H. Idris, S. Hardi and M. Z. Hassan, “Teaching Distance Relay Using Matlab/Simulink Graphical User Interface”, Malaysian Technical Universities Conference on Engineering and Technology,

November 2012.

[4] L. C. Wu, C. W. Liu and C. S. Chen, “Modeling and testing of a digital distance relay using Matlab/Simulink”, IEEE 2005.

[5] The Math Works, Inc., “SimPowerSystems user‟s guide”, Version 4.6, 2008.

Modified Phase-Shifted PWM Scheme for Improved Reliability in CHB MI

modified phase-shifted pwm scheme for reliability improvement in cascaded h-bridge multilevel inverters

ABSTRACT:

The cascaded H-bridge multilevel inverter (CHMI) is a modular structure that consists of many power semiconductor switches.With this increase in the number of power semiconductor switches, it is hard to predict and handle the failure of the devices, and hence reliability of CHMI decreases. The major cause of power semiconductor switch failure is junction temperature that is produced by power losses. The study proposes a multi-carrier pulse-width modulation (PWM) scheme for reduction in switching losses of CHMI.

PWM

One leg conducts switching operation with high frequency, while the other leg conducts switching operation with fundamental frequency. The switching operations with different frequencies cause unbalanced switching loss to each leg. Additionally, the switching frequency of the two legs is alternated to evenly distribute switching losses and junction temperature. Simulation and experimental results verify the performance of the proposed PWM scheme.

KEYWORDS:

  1. Cascaded H-bridge multilevel inverter
  2.  Phase-shifted pulse-width modulation scheme
  3. Reliability of power semiconductor switch
  4. Switching loss reduction

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Figure 1. Circuit Configuration of Three-Phase CHMI.

EXPECTED SIMULATION RESULTS:

Figure 2. Simulation of Conventional PS-PWM Scheme.

Figure 3. Simulation of Proposed PS-PWM Scheme In 5-Level CHMI.

Figure 4. Simulation of Proposed PS-PWM Scheme In 9-Level CHMI.

CONCLUSION:

This paper proposes a modulation method for a 5-level three phase CHMI to extend the life-time and improve reliability of power semiconductor switches. The proposed method is based on the PS-PWM scheme and decreased power losses via the clamped modulation period. The clamped signal reduces power loss, and other signal is reconfigured to maintain the quality of output waveforms such as the level of output voltage.

CHMI

Reduced power losses decrease the temperature of the power semiconductor switch, and thus the expected life-time of the power semiconductor switch is extended by using the proposed modulation method.

SWITCHING

The rotation method with 1/4 period is applied to proposed scheme for even switching loss and temperature among switches. The performance of the proposed method is verified via simulation and experimental results.

REFERENCES:

[1] B.Wu, High-Power Converter and AC Drives. Hoboken, NJ, USA:Wiley, 2006.

[2] D. Karwatzki and A. Mertens, “Generalized control approach for a class of modular multilevel converter topologies,” IEEE Trans. Power Electron., vol. 33, no. 4, pp. 2888_2900, Apr. 2018.

[3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B.Wu, J. Rodriguez, M. A. Pérez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553_2580, Aug. 2010.

[4] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel Voltage-Source-Converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930_2945, Dec. 2007.

[5] G. P. Adam, I. A. Abdelsalam, K. H. Ahmed, and B.W.Williams, “Hybrid multilevel converter with cascaded H-bridge cells for HVDC applications: Operating principle and scalability,” IEEE Trans. Power Electron., vol. 30, no. 1, pp. 65_77, Jan. 2015.

A Single-Carrier-Based its Pulse-Width Modulation Template for Cascaded H-bridge

A Single-Carrier-Based Pulse-Width Modulation Template for Cascaded H-Bridge Multilevel Inverters

ABSTRACT:

Multiplicity of the triangular carrier signals is a criterion for the extension of sinusoidal pulse width modulation, SPWM, to a number of output voltage levels per phase-leg in cascaded H-bridge (CHB) multilevel inverter (MLI). Considering medium and high voltage applications where appreciable number of output voltage levels from CHB MLI is needed, commensurate high number of carrier signals in either classical level- or phase-shifted SPWM scheme for this inverter is inevitable.

PWM

High-quality output waveforms from CHB MLI system demands precise synchronization of these multi-carrier signals. Sampling issues, memory constraints and computational delays pose difficulties in achieving this synchronization for real-time digital implementation. This study presents a PWM template for CHB MLI. The developed control concept generates adequate modulation templates for CHB inverter wherein a sinusoidal modulating waveform is modified to fit in a single triangular carrier signal range.

CHB INVERTER

These templates can be used on CHB inverter of any level with no further control modification. Nearly even distribution of switching pulses, equal sharing of the overall real power among the constituting power switches and enhanced output voltage quality were achieved with the proposed modulation. For a 3-phase, 7-level CHB, Pulse-Width Modulation simulation and experimental results, for an R-L load, were presented.

KEYWORDS:

  1. Cascaded H-bridge inverter
  2. Sinusoidal pulse-width modulation
  3. Total harmonic distortion

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Figure 1. Cascaded H-Bridge Multilevel Inverter Power Circuit.

EXPECTED SIMULATION RESULTS:

Figure 2. Simulated Output Voltage And Current Waveforms Of The 7-Level Chb Mli With The Proposed Pwm Scheme. (A) Phase A Individual H-Bridge Output Voltages, (B) Phase-Leg Voltages, (C) Line Voltages, (D) Line Currents.

Figure 3. Simulated Dc-Link Voltages, Fft Analyses Of The Phase-Leg And Line Voltage Waveforms And Real Output Power Waveforms. (A) Dc-Link Voltages For The Whole Phases, (B) Fft Analysis Of The Phase-Leg Voltage Waveform From Ipd, Ps And Proposed Modulation Schemes, (C) Fft Analysis Of The Line Voltage Waveform From Ipd, Ps And Proposed Modulation Schemes, (D) Real Output Power Waveforms Of The Individual H-Bridges With The Proposed Spwm Scheme.

Figure 4. Experimental Output Voltages And Currents. (A) Each H-Bridge’s Output Voltage In Phase `A’, (B Phase-Leg Output Voltages In All The Phases, (C) Output Line Voltages, (D) Output Line Currents.

Figure 5. Experimental Dynamic Responses Of The Inverter System: (A), (B) Change In The Modulation Index Value At Constant Input Dc-Link Voltages; (C), (D) Change In The Input Dc-Link Voltages At Constant Output Load Current.

CONCLUSION:

Presented in this paper is a hybridized single carrier-based pulse width modulation scheme for cascaded H-bridge multilevel inverter. Its operational concept wherein a sinusoidal modulating waveform is Pulse-Width Modulation modified to fit in a single triangular carrier signal range in order to generate the desired output waveform template for the MLI has been explained in detail. The principle of generating the modulating templates is a furtherance of earlier established modulation approaches for multilevel inverters.

H-BRIDGE

It has been shown that the generation of the modulating templates is a clear demonstration of the extension of the well-known bipolar PWM to multi-cascaded H-bridge units. Once the templates are generated, it can be used on CHB inverter of any level with no further control modification; only the parameter N need to be specified Pulse-Width Modulation . From industrial point of view, the presented concept of MWT will find its application in large number of cascaded H-bridge systems because with the proposed modulation, the inverter control system becomes insensitive to the traditional concept of multiplicity of carrier waves as the number of inverter level increases.

SPWM

This will be highly advantageous since the extra control effort of carrier synchronization will be by-passed in the control algorithm Pulse-Width Modulation. The proposed SPWM ensures nearly even distribution of switching pulses among the constituting power switches using a reverse-voltage-sorting comparison algorithm. Consequently, the real power variations in the entire cascaded H-bridges are kept within a very narrow band.

CHB

From our findings, the proposed control approach results in a hybrid modulation scheme that mediates between the phase and level-shifted carrier-based SPWM techniques; thereby inheriting the good features in these two modulation schemes. The performance of the proposed SPWM scheme has been presented through scaled down simulations and experiments on a 3-phase, 7-level CHB inverter; results have been adequately presented.

REFERENCES:

[1] S. K. Chattopadhyay and C. Chakraborty, “Full-bridge converter with naturally balanced modular cascaded H-bridge waveshapers for offshore HVDC transmission,” IEEE Trans. Sustain. Energy, vol. 11, no. 1, pp. 271_281, Jan. 2020, doi: 10.1109/TSTE.2018.2890575.

[2] X. Zeng, D. Gong, M. Wei, and J. Xie, “Research on novel hybrid multilevel inverter with cascaded H-bridges at alternating current side for highvoltage direct current transmission,” IET Power Electron., vol. 11, no. 12, pp. 1914_1925, Oct. 2018, doi: 10.1049/iet-pel.2017.0925.

[3] R. K. Varma and E. M. Siavashi, “PV-STATCOM: A new smart inverter for voltage control in distribution systems,” IEEE Trans. Sus- tain. Energ., vol. 9, no. 4, pp. 1681_1691, Oct. 2018, doi: 10.1109/ TSTE.2018.2808601.

[4] P. Sotoodeh and R. D. Miller, “Design and implementation of an 11- level inverter with FACTS capability for distributed energy systems,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 2, no. 1, pp. 87_96, Mar. 2014, doi: 10.1109/JESTPE.2013.2293311.

[5] A. Ahmed, M. S. Manoharan, and J.-H. Park, “An efficient single-sourced asymmetrical cascaded multilevel inverter with reduced leakage current suitable for single-stage PV systems,” IEEE Trans. Energy Convers., vol. 34, no. 1, pp. 211_220, Mar. 2019, doi: 10.1109/TEC.2018.2874076.

A Generalized Multilevel Inverter Topology with Reduction of Total Standing Voltage

ABSTRACT:

This paper presents a new multilevel inverter topology with reduced active switches and total standing voltage. The proposed topology can generate a high number of voltage levels in the symmetric configuration. This topology intuitively generates positive and negative cycles without an additional H-bridge unit, which considerably reduces the total standing voltage of the inverter.

CASCADED

A cascaded structure is developed from the proposed topology to create higher voltage levels. To show the novelty of the proposed topology, a thorough comparison between the available and the proposed topologies in terms of the number of switches, standing voltages, and dc-sources is presented. Furthermore, the power loss analysis is carried out for various load values. The feasibility of the proposed nine-level inverter is verified with simulation and experimental results.

KEYWORDS:

  1. Multilevel inverter
  2. Inverter
  3. Blocking voltage
  4. Cascaded structure
  5. Reduced power components

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Figure 1. Proposed h-type topology generating 5L.

EXPECTED SIMULATION REUSLTS:

Figure 2. Simulation results of the proposed 9L inverter for R = 30 W, L = 40mH a) Output voltage waveform with FFT spectrum, b) Output Current with FFT spectrum and (c) blocking voltage on switches P2, S3, S1, S6, S4.

Figure 3. Experimental results of Output voltage and current waveform for proposed 9L inverter (a) at load 30 W-40mH, dynamic load changes (b) from 50 W-60 mH to 30 W-40 mH, (c) from 30 W-40 mH to no-load (d) from no-load to 50 􀀀 60 mH and modulation index variations (e) from 0.4 to 0.6 and (f) from 0.6 to 1.0.

Figure 4. PCond;T , PCond;D , PSw;T , and PSw;D (a) at 0:5kW (b) at 1:0kW, (c) at 1:5kW\ (d) at 2:5kW (e) at 5:5kW and (f) Power Efficiency and Loss

CONCLUSION:

The proposed topology used lower number of power electronics components and reduced dc-sources. Further, the maximum voltage stress on the switch is reduced to 4Vdc for any number of voltage levels in symmetric configuration which is more suitable for medium voltage applications. The simulated and experimental results are presented for various load values.

AC

The sudden load changes and modulation index variations are applied to the proposed topology and it corresponding results are given. Further, the power loss and efficiency of propose topology presented for various load power. It is confirming that the proposed topology is more suitable various load changing applications like AC drives, grid connected PV system etc.

REFERENCES:

[1] S. A. Teston, M. Mezaroba, and C. Rech, “Anpc inverter with integrated secondary bidirectional dc port for ess connection,” IEEE Transactions on Industry Applications, vol. 55, no. 6, pp. 7358–7367, 2019.

[2] Jing Huang and K. A. Corzine, “Extended operation of flying capacitor multilevel inverters,” IEEE Transactions on Power Electronics, vol. 21, no. 1, pp. 140–147, 2006.

[3] S. P. Gautam, “Novel h-bridge-based topology of multilevel inverter with reduced number of devices,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 7, no. 4, pp. 2323–2332, 2019.

[4] S. A. A. Ibrahim, A. Palanimuthu, and M. A. J. Sathik, “Symmetric switched diode multilevel inverter structure with minimised switch count,” The Journal of Engineering, vol. 2017, no. 8, pp. 469–478, 2017.

[5] S. S. Lee, M. Sidorov, N. R. N. Idris, and Y. E. Heng, “A symmetrical cascaded compact-module multilevel inverter (ccm-mli) with pulse width modulation,” IEEE Transactions on Industrial Electronics, vol. 65, no. 6, pp. 4631–4639, 2018.

Active Power Filter for Harmonic Mitigation of Power Quality Issues in Grid Integrated Photovoltaic Generation System

ABSTRACT:

Single phase supply scheme tied with Photovoltaic arrangement (PV) employed on perturbed & observed (P&O) maximum energy point tracking technique with shunt active power filter allied to a rectifier feed R-L nonlinear load. The traditional Perturbed & Observed technique maximum energy point tracking topology is applied to attained maximum output power from Photovoltaic array(PVA), Proportional Integral conventional controller with phase detector (PD) phase locked loop (PLL) synchronization are executed to produce reference current.

PWM

It provide at control unit of pulse width modulation topology( PWM) is utilized in inverter to get steady output voltage. Self supported DC bus PWM converter is regulated from PV array. In proposed architecture is minimized total harmonic pollution existing in supply current owing to power electronic load (PEL). Total current harmonic pollution (THDi) is compensated using dynamic filter shunt active power filter (SAPF) and power factor obtain better later than compensation. Hence, reactive power (KVAR) is delivered through system decrease and active power (KW) enhance. The suggested scheme has been implemented by way of MATLAB/SIMULINK 2015(a) environment.

KEYWORDS:

  1. Shunt Active Power Filter (SAPF)
  2. Photovoltaic Array (PVA)
  3. Proportional Integral controller
  4. Pulse width Modulated (PWM) Converter
  5. Maximum Power Point Tracking (P & O) Scheme

SOFTWARE: MATLAB/SIMULINK

SCHEMATIC DIAGRAM:

Fig.1 Suggested system schematic.

EXPECTED SIMULATION RESULTS:

Fig.2. PV array voltage before boosting.

Fig.3. DC link voltage

Fig.4. Power Factor

Fig.5. Source currents before compensation.

Fig.6. SAPF filter current.

Fig.7.Source current after comopensation as after 0.1 sec.

Fig.8. Graphical representation of active power

Fig.9. Graphical representation of reactive power

Fig.10. Source current harmonic spectrum befor compensation with

rectifier non linear diode load.

Fig.11. Source current harmonic graph after SAPF application.

CONCLUSION:

 In this research paper SAPF based on phase detector circuit (PLL) for unit vector generation with traditional PI controller is implemented. This controller regulates DC side voltage, reference current generated by PI conventional controller and positive progression predictor PLL synchronization unit.

HBCC

Hysteresis band current control(HBCC) is employed to produce gate signal for voltage source inverter (VSI). The source current THD is abridged to fewer than 5% that is in accordance IEEE-519 standards for harmonic. Active power is improved by dynamic filtering using SAPF and decrease in reactive power consequently, power factor level is become finer.

REFERENCES:

[1] M. Singh, V. Khadkikar, A. Chandra, and R. K. Varma,“Grid Interconnection of Renewable Energy Sources at the Distribution Level With Power-Quality Improvement Features” IEEE Transactions on Power Delivery, vol. 26, no. 1, January 2011.

[2] S. Agrawal, Seemant Chorsiya, D.K Palwalia, “Hybrid Energy Management System design with Renewable Energy Sources (Fuel Cells, PV Cells and Wind Energy): A Review”, IJSET, vol. 6, no. 3, pp.174-177, 2018. DOI : 10.5958/2277 1581.2017.00104.8.

[3] M. G. Villalva, J. R. Gazoli and E. R. Filho, “Modeling and circuitbased simulation of photovoltaic arrays”, Brazilian Power Electronics Conference, Bonito-Mato Grosso do Sul, pp. 1244-1254, 2009.

[4] S. Agrawal and D. K. Palwalia, “Analysis of standalone hybrid PVSOFC- battery generation system based on shunt hybrid active power filter for harmonics mitigation.” IEEE Power India International Conference (PIICON) pp. 1-6, 2016.

[5] M. M. Hashempour, M. Savaghebi, J. C. Vasquez and J. M. Guerrero, “A Control Architecture to Coordinate Distributed Generators and Active Power Filters Coexisting in a Microgrid”, IEEE Transactions on Smart Grid, vol. 7, no. 5, pp. 2325-2336, Sept. 2016.

A Novel V2V Charging Method Addressing the Last Mile Connectivity

ABSTRACT:

One of the main drawbacks in adopting EV vehicles is the last mile connectivity issue. There is always a chance that the user/rider may get stranded without EV charge and no EV charging stations nearby. With the aim of solving such an exigency, this paper proposes a novel V2V charging technique which allows charge transfer between two EVs off the grid, and discusses its modes of operation. Non-isolated bidirectional DC-DC converters with average current control technique are simulated in a MATLAB/Simulink environment to verify and validate the efficiency and charging time for the proposed charging technique.

KEYWORDS:

  1. V2V charging
  2. Bi-directional converter
  3. Pricing strategy

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Figure 1: Block diagram of V2V technology

EXPECTED SIMULATION RESULTS:

Figure 2: SOC% plots where higher SOC battery is charging and lower SOC battery is discharging

Figure 3: SOC% plots where higher SOC battery is discharging and lower SOC battery is charging

CONCLUSION:

A V2V charging scheme is proposed to synchronize the charging between two electric vehicles. This is particularly needed when an EV user is left stranded without battery charge and with no access to EV charging station. In this scenario, the proposed model allows another EV user to assist the stranded EV by charging from his EV thus solving last mile connectivity issues. The proposed model consists of a dual converter in the electric vehicle which enables fast DC charging or discharging. Extensive MATLAB simulation results on the model proves that the proposed work is capable of charging an EV from another under average current control method. The efficiency, SOC status and charging time for the proposed method is also analyzed. From the analysis it is evident that as the SOC difference increases the efficiency obtained also increases. To reduce the charging time and to enhance the efficiency average current control method is simulated and analyzed. The results obtained are presented and the results confirm the effectiveness of the proposed work.

V2V energy transfers which were reported in the earlier literature uses the concept of connected ad-hoc networks present in parking lots etc., where the vehicles parked in the parking lot are used for energy transfer through a connected bus in the parking lot itself. The term ‘novel’ has been used here as the issue of EV being left stranded without battery charge and with no access to charging station is not addressed anywhere in the literature and also the technique of using cascaded bi-directional converters for charging one vehicle from the other vehicle adds novelty to the V2V energy transfer. Cascaded Bidirectional converters can even facilitate the charge transfer when the electric vehicles battery voltage levels are different, that’s why cascaded converters has been employed.

REFERENCES:

[1] Markel, T., Saxena. S, Kahl. K, Pratt. R, “Multi-Lab EV Smart Grid Integration Requirements Study: Providing Guidance on Technology Development and Demonstration”, National Renewable Energy Laboratory. Retrieved 2016-03-08, 2005.

[2] Liu, Wei-Shih, Jiann-Fuh Chen, Tsorng-Juu Liang, Ray-Lee Lin, and Ching-Hsiung Liu, “Analysis, design, and control of bidirectional cascaded configuration for a fuel cell hybrid power system,” IEEE Transactions on Power Electronics 25,Vol. 6, 2010, pp no:- 1565-1575.

[3] Akshya, S., Anjali Ravindran, A. Sakthi Srinidhi, Subham Panda, and Anu G. Kumar, “Grid integration for electric vehicle and photovoltaic panel for a smart home.” 2017 International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 1-8, 2017.

[4] Nagar, Ishan, M. Rajesh, and P. V. Manitha, “A low cost energy usage recording and billing system for electric vehicle,” International Conference on Inventive Communication and Computational Technologies (ICICCT), pp. 382-384, 2017.

[5] Rajalakshmi, B., U. Soumya, and Anu G. Kumar. “Vehicle to grid bidirectional energy transfer: Grid synchronization using Hysteresis Current Control”, International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 1-6, 2017.

A New Five-Level Buck-Boost Active Rectifier

ABSTRACT:

In this paper a new single-phase five-level buck boost active rectifier is introduced called capacitor tied switches (CTS). The proposed rectifier has two independent DC outputs that can be connected to two different loads. Different switching states and the average mode of the proposed topology are analyzed to design the associated controller aims at regulating the two output DC voltages, generating five-level voltage at the input of the rectifier and finally draw unity power factor and sinusoidal current from AC grid. From AC grid view, the rectifier works in boost mode however the generated DC voltage can be split into two separate outputs which may be less than the AC peak voltage or even more leads to work in both buck and boost operation mode. Full simulation results are shown and analyzed to validate the effective operation and good dynamic performance of the proposed five-level buck-boost rectifier.

KEYWORDS:

  1. Multilevel converter
  2. Packed U-Cell
  3. Active PFC rectifier
  4. Buck-boost rectifier
  5. Capacitor Tied Switches (CTS)

SOFTWARE: MATLAB/SIMULINK

PROPOSED DIAGRAM:

Figure 1: proposed five-level buck-boost PFC rectifier (CTS)

EXPECTED SIMULATION RESULTS:

Figure 2: simulation results during change in DC voltages from 100 V to 200 V (transition between buck and boost modes). a) vs and is *current waveform multiplied by 4 b) power factor c) input voltage of the CTS rectifier Vad d) V1 e) V2

Figure 3: harmonic spectrum of Vad and is in buck mode (100 V DC output)

Figure 4: harmonic spectrum of Vad and is in boost mode (200 V DC output)

Figure 5: simulation results during load changes in buck mode. A) vs and is *current waveform is multiplied by 15 b) input voltage of the CTS rectifier Vad

c) V1 d) i1 e) V2 f) i2

Figure 6: simulation results during the loads changes in boost mode. A) vs and is *current waveform is multiplied by 15 b) input voltage of the CTS rectifier Vad

c) V1 d) i1 e) V2 f) i2

CONCLUSION:

In this paper a new topology of buck-boost active rectifier has been introduced based on slight modification of the third U-cell of the PUC original design. The proposed rectifier called CTS includes six switches tied by two capacitors as two output independent DC terminals and generates five-level voltage waveform at the input. The latter draw low harmonic current in-phase with the grid voltage making the operation at unity power factor rectifier easy in both buck and boost mode. This topology does not need additional bulky filters while switching at low frequency which constitute a big advantage of the presented CTS rectifier. Simulation results including regulated DC voltages, high power factor, and low supply THD current mainly obtained by the five-level rectifier input voltage. Moreover, good dynamic performance, fast response and reliable operation of the implemented controller and CTS converter topology were proven and discussed in details.

REFERENCES:

[1] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, “A review of single-phase improved power quality ACDC converters,” Industrial Electronics, IEEE Transactions on, vol. 50, pp. 962-981, 2003.

[2] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, “A review of three-phase improved power quality AC-DC converters,” Industrial Electronics, IEEE Transactions on, vol. 51, pp. 641-660, 2004.

[3] H. Abu-Rub, M. Malinowski, and K. Al-Haddad, Power electronics for renewable energy systems, transportation and industrial applications: John Wiley & Sons, 2014.

[4] L. Yacoubi, K. Al-Haddad, L.-A. Dessaint, and F. Fnaiech, “Linear and nonlinear control techniques for a three-phase three-level NPC boost rectifier,” Industrial Electronics, IEEE Transactions on, vol. 53, pp. 1908-1918, 2006.

[5] L. Yacoubi, K. Al-Haddad, L.-A. Dessaint, and F. Fnaiech, “A DSPbased implementation of a nonlinear model reference adaptive control for a three-phase three-level NPC boost rectifier prototype,” Power Electronics, IEEE Transactions on, vol. 20, pp. 1084-1092, 2005.