Single-phase multilevel inverter topologies with self-voltage balancing capabilities


In this study, two new structures of single-phase hybrid multilevel inverter are proposed for both symmetrical and asymmetrical configurations that can be employed in drives and control of electrical machines and connection of renewable energy sources. The proposed configuration uses a less number of semiconductor devices and DC sources as compared with conventional and newly developed topologies which lead to a reduction in cost and installation area. The proposed topology poses a vital advantage of self-voltage balancing of its capacitor voltage regardless of load type, load dynamics and modulation index. Also, the proposed topology is expanded in a cascaded fashion which reduces the complexity and improves the performance significantly. A wide range of comparison is done with conventional and newly developed topologies to show the superior performance of proposed topologies regarding a total number of switches and DC sources. The multi-carrier pulsewidth modulation strategy is adopted for generating switching pulses for respective switches. A laboratory prototype is developed for testing the performance of the proposed topology for 9-level and 17-level inverters.





Fig. 1. Configuration of the proposed topology-I

Fig. 2 Configuration of the proposed topology-II












Fig. 3 (a) 9-Level waveforms of topology-I at two different switching frequencies of 5 kHz and 100 Hz, (b) 17-Level waveforms of topology-II at 5 kHz switching frequency, (c) Sudden load transition, (d) Sudden change in modulation index, i.e. from unity to 0.5



This paper proposes two new hybrid topologies of symmetrical and asymmetrical MLI with the self-voltage balancing of its capacitor voltage and with a reduced number of devices. For obtaining the maximum number of output levels in asymmetrical configuration, a new algorithm is proposed. The proposed topologies have been tested experimentally for 9-level and 17-level inverters under different switching frequencies. For effectively demonstrating the self-voltage balancing phenomenon of capacitor voltage, the proposed topologies have been tested under non-linear load, reactive load, under different modulation index and different load transition. A wide range of comparison is drawn between the proposed topologies, the conventional and the newly developed topologies which show that the proposed topologies require the least number of switches and DC sources as compared with other topologies.



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