A Single-Phase Cascaded Multilevel Inverter Composed of Four-Level Sub-multilevel Cells


This paper presents a novel cascaded multilevel inverter topology. The series connection of proposed basic cells is the main core of this topology. Different methods to determine the values of DC voltage sources in cells are investigated. Advantages and disadvantages of this topology in comparison with classical topologies are discussed. Symmetric and asymmetric structures of this topology are well analyzed through simulations.


  1. Cascaded multilevel inverter
  2. Single phase



Fig.. 1. General scheme of proposed cascaded multilevel inverter


Fig. 2. Simulation results of two-cell proposed inverter Symmetric design: (a) va (b) Vaal and iout(c) THD Asymmetric design: (d) va (e) Vout and iout(f) THD

Fig.3.The blocking voltage of  switches(a) S11 and S12 (b)S21 and  S22  (c)S31 and S32 (d)S41 and S42 (e) Sa (f) Sb  (g) T1 and T4 (h)  T2 and T3.


In this paper a new structure for multilevel inverters based on series connection of four-level sub-multilevel basic cells is proposed. The H-bridge inverter and additional circuit have been added to the basic form of the proposed inverter in order to generate positive and negative polarities and facilitate the symmetric and asymmetric implementations regarding the values of the dc sources. Different methods are suggested to choose the values of the dc sources and they are appraised by comparison studies with classical cascaded H-bridge inverter. The results of this survey illustrate the fact that the number of switches and the total blocking voltage of the inverter are reduced for the proposed topology compared to the classical ones. Finally, the simulation results on a two-cell inverter with symmetric and asymmetric implementation confirm the proper performance of the proposed topology.


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