This paper presents a novel ac-dc power factor correction (PFC) power conversion architecture for single-phase grid interface. The proposed architecture has significant advantages for achieving high efficiency, good power factor, and converter miniaturization, especially in low-to-medium power applications.
The architecture enables twice-line-frequency energy to be buffered at high voltage with a large voltage swing, enabling reduction in the energy buffer capacitor size, and elimination of electrolytic capacitors. While this architecture can be beneficial with a variety of converter topologies
Power Factor Correction It is especially suited for system miniaturization by enabling designs that operate at high frequency (HF, 3 – 30 MHz). Moreover, we introduce circuit implementations that provide efficient operation in this range. The proposed approach is demonstrated for an LED driver converter operating at a (variable) HF switching frequency (3 – 10 MHz) from 120Vac,and supplying a 35Vdc output at up to 30W.
Power Factor Correction The prototype converter achieves high efficiency (92 %) and power factor (0.89), and maintains good performance over a wide load range. Owing to architecture and HF operation, the prototype achieves a high ‘box’ power density of 50W/ in3 (‘displacement’ power density of 130W/ in3), with miniaturized inductors, ceramic energy buffer capacitors, and a small-volume EMI filter.
- High frequency
- Power factor correction PFC
- Power factor
- Electromagnetic interference EMI
Fig. 1: The proposed grid interface power conversion architecture comprises a line-frequency rectifier, a stack of capacitors, a set of regulating converters, and a power combining converter.
EXPECTED SIMULATION RESULTS:
Fig. 2: Operation of the prototype converter from a 120Vac line voltage to a 35Vdc output. Each figure illustrates voltage and / or current waveforms over the ac line cycle: (a) the measured 120Vac line input voltage and the measured voltages across the capacitor stack (output of the bridge rectifier) (b) the measured voltages across C1 and across C2 for a delivered output power of 29W (c) the measured input current waveform at 29W output power (d) the measured input current waveform at 20W output power (e) the output voltage waveform at 29W output power (f) the switched capacitor voltage waveform at 29W output power.
A new single-phase grid interface ac-dc PFC architecture is introduced and experimentally demonstrated. In addition to enabling high efficiency and good power factor, this PFC architecture is particularly advantageous in that it enables extremely high operating frequencies (into the HF range) and reduction in energy buffer capacitor values, each of which contributes to converter miniaturization.
The proposed stacked combined architecture significantly decreases the voltage stress of the active and passive devices and reduces characteristic impedance levels, enabling substantial increases in switching frequency when utilized with appropriate converter topologies.
Power Factor Correction Moreover, good power factor is achieved while dynamically buffering twice-line-frequency ac energy with relatively small capacitors operating with large voltage swing. The prototype converter achieves high efficiency and good power factor over a wide power range, and meets the CISPR Class-B Conducted electromagnetic interference (EMI) Limits.
Power Factor Correction The prototype converter based on the architecture and selected high-frequency circuit topology demonstrates an approximate factor of 10 reduction in volume compared to typical designs. The prototype has a very high ‘box’ power density of 50W=in3 (‘displacement’ power density of 130W=in3) with miniaturized inductors, a small volume of EMI filter, and ceramic energy buffer capacitors.
Power Factor Correction Lastly, as described in the appendix, the proposed architecture can be realized in various ways (e.g., with alternative topologies) to realize features such as galvanic isolation and universal input range.
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