A Single-Carrier-Based its Pulse-Width Modulation Template for Cascaded H-bridge

A Single-Carrier-Based Pulse-Width Modulation Template for Cascaded H-Bridge Multilevel Inverters


Multiplicity of the triangular carrier signals is a criterion for the extension of sinusoidal pulse width modulation, SPWM, to a number of output voltage levels per phase-leg in cascaded H-bridge (CHB) multilevel inverter (MLI). Considering medium and high voltage applications where appreciable number of output voltage levels from CHB MLI is needed, commensurate high number of carrier signals in either classical level- or phase-shifted SPWM scheme for this inverter is inevitable.


High-quality output waveforms from CHB MLI system demands precise synchronization of these multi-carrier signals. Sampling issues, memory constraints and computational delays pose difficulties in achieving this synchronization for real-time digital implementation. This study presents a PWM template for CHB MLI. The developed control concept generates adequate modulation templates for CHB inverter wherein a sinusoidal modulating waveform is modified to fit in a single triangular carrier signal range.


These templates can be used on CHB inverter of any level with no further control modification. Nearly even distribution of switching pulses, equal sharing of the overall real power among the constituting power switches and enhanced output voltage quality were achieved with the proposed modulation. For a 3-phase, 7-level CHB, Pulse-Width Modulation simulation and experimental results, for an R-L load, were presented.


  1. Cascaded H-bridge inverter
  2. Sinusoidal pulse-width modulation
  3. Total harmonic distortion



Figure 1. Cascaded H-Bridge Multilevel Inverter Power Circuit.


Figure 2. Simulated Output Voltage And Current Waveforms Of The 7-Level Chb Mli With The Proposed Pwm Scheme. (A) Phase A Individual H-Bridge Output Voltages, (B) Phase-Leg Voltages, (C) Line Voltages, (D) Line Currents.

Figure 3. Simulated Dc-Link Voltages, Fft Analyses Of The Phase-Leg And Line Voltage Waveforms And Real Output Power Waveforms. (A) Dc-Link Voltages For The Whole Phases, (B) Fft Analysis Of The Phase-Leg Voltage Waveform From Ipd, Ps And Proposed Modulation Schemes, (C) Fft Analysis Of The Line Voltage Waveform From Ipd, Ps And Proposed Modulation Schemes, (D) Real Output Power Waveforms Of The Individual H-Bridges With The Proposed Spwm Scheme.

Figure 4. Experimental Output Voltages And Currents. (A) Each H-Bridge’s Output Voltage In Phase `A’, (B Phase-Leg Output Voltages In All The Phases, (C) Output Line Voltages, (D) Output Line Currents.

Figure 5. Experimental Dynamic Responses Of The Inverter System: (A), (B) Change In The Modulation Index Value At Constant Input Dc-Link Voltages; (C), (D) Change In The Input Dc-Link Voltages At Constant Output Load Current.


Presented in this paper is a hybridized single carrier-based pulse width modulation scheme for cascaded H-bridge multilevel inverter. Its operational concept wherein a sinusoidal modulating waveform is Pulse-Width Modulation modified to fit in a single triangular carrier signal range in order to generate the desired output waveform template for the MLI has been explained in detail. The principle of generating the modulating templates is a furtherance of earlier established modulation approaches for multilevel inverters.


It has been shown that the generation of the modulating templates is a clear demonstration of the extension of the well-known bipolar PWM to multi-cascaded H-bridge units. Once the templates are generated, it can be used on CHB inverter of any level with no further control modification; only the parameter N need to be specified Pulse-Width Modulation . From industrial point of view, the presented concept of MWT will find its application in large number of cascaded H-bridge systems because with the proposed modulation, the inverter control system becomes insensitive to the traditional concept of multiplicity of carrier waves as the number of inverter level increases.


This will be highly advantageous since the extra control effort of carrier synchronization will be by-passed in the control algorithm Pulse-Width Modulation. The proposed SPWM ensures nearly even distribution of switching pulses among the constituting power switches using a reverse-voltage-sorting comparison algorithm. Consequently, the real power variations in the entire cascaded H-bridges are kept within a very narrow band.


From our findings, the proposed control approach results in a hybrid modulation scheme that mediates between the phase and level-shifted carrier-based SPWM techniques; thereby inheriting the good features in these two modulation schemes. The performance of the proposed SPWM scheme has been presented through scaled down simulations and experiments on a 3-phase, 7-level CHB inverter; results have been adequately presented.


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A Generalized Multilevel Inverter Topology with Reduction of Total Standing Voltage


This paper presents a new multilevel inverter topology with reduced active switches and total standing voltage. The proposed topology can generate a high number of voltage levels in the symmetric configuration. This topology intuitively generates positive and negative cycles without an additional H-bridge unit, which considerably reduces the total standing voltage of the inverter.


A cascaded structure is developed from the proposed topology to create higher voltage levels. To show the novelty of the proposed topology, a thorough comparison between the available and the proposed topologies in terms of the number of switches, standing voltages, and dc-sources is presented. Furthermore, the power loss analysis is carried out for various load values. The feasibility of the proposed nine-level inverter is verified with simulation and experimental results.


  1. Multilevel inverter
  2. Inverter
  3. Blocking voltage
  4. Cascaded structure
  5. Reduced power components



Figure 1. Proposed h-type topology generating 5L.


Figure 2. Simulation results of the proposed 9L inverter for R = 30 W, L = 40mH a) Output voltage waveform with FFT spectrum, b) Output Current with FFT spectrum and (c) blocking voltage on switches P2, S3, S1, S6, S4.

Figure 3. Experimental results of Output voltage and current waveform for proposed 9L inverter (a) at load 30 W-40mH, dynamic load changes (b) from 50 W-60 mH to 30 W-40 mH, (c) from 30 W-40 mH to no-load (d) from no-load to 50 􀀀 60 mH and modulation index variations (e) from 0.4 to 0.6 and (f) from 0.6 to 1.0.

Figure 4. PCond;T , PCond;D , PSw;T , and PSw;D (a) at 0:5kW (b) at 1:0kW, (c) at 1:5kW\ (d) at 2:5kW (e) at 5:5kW and (f) Power Efficiency and Loss


The proposed topology used lower number of power electronics components and reduced dc-sources. Further, the maximum voltage stress on the switch is reduced to 4Vdc for any number of voltage levels in symmetric configuration which is more suitable for medium voltage applications. The simulated and experimental results are presented for various load values.


The sudden load changes and modulation index variations are applied to the proposed topology and it corresponding results are given. Further, the power loss and efficiency of propose topology presented for various load power. It is confirming that the proposed topology is more suitable various load changing applications like AC drives, grid connected PV system etc.


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