Enhancing power cycling capability of power semiconductor devices is highly demanded in order to increase the long term reliability of multilevel inverters. Ageing of power switches and their cooling systems leads to their accelerated damage due to excess power losses and junction temperatures. Therefore, thermal stresses relief (TSR) is the most effective solution for lifetime extension of power semiconductor devices. This paper presents a new thermal stresses relief carrier-based pulse width modulation (TSRPWM) strategy for extending the lifetime of semiconductor switches in single-phase multilevel inverters. The proposed strategy benefits the inherent redundancy among switching states in multilevel inverters to optimally relieve the thermally stressed device. The proposed algorithm maintains the inverter operation without increased stresses on healthy switches and without reduction of the output power ratings. In addition, the proposed algorithm preserves voltage balance of the DC-link capacitors. The proposed strategy is validated on single phase five level T-type inverter system with considering different locations of thermal stresses detection. Experimental prototype of the selected case study is built to verify the results. Moreover, comparisons with the most featured strategies in literature are given in detail.
Fig. 1. A schematic diagram of PWM controlled full bridge n-level T-type inverter
EXPECTED SIMULATION RESULTS
Fig. 2. Simulation results of the proposed strategy at TSD in SA11 at mi=0.85.
Fig. 3. Simulation results of the proposed strategy at TSD in SA11 at mi=0.45.
Fig. 4. Simulation results of the proposed TSRPWM strategy at TSD in SA12 and mi=0.85.