A Multilevel Inverter Structure based on Combination of Switched-Capacitors and DC Sources


This paper presents a switched-capacitor multilevel inverter (SCMLI) combined with multiple asymmetric DC sources. The main advantage of proposed inverter with similar cascaded MLIs is reducing the number of isolated DC sources and replacing them with capacitors. A self-balanced asymmetrical charging pattern is introduced in order to boost the voltage and create more voltage levels. Number of circuit components such as active switches, diodes, capacitors, drivers and DC sources reduces in proposed structure. This multi-stage hybrid MLI increases the total voltage of used DC sources by multiple charging of the capacitors stage by stage. A bipolar output voltage can be inherently achieved in this structure without using single phase H-bridge inverter which was used in traditional SCMLIs to generate negative voltage levels. This eliminates requirements of high voltage rating elements to achieve negative voltage levels. A 55-level step-up output voltage (27 positive levels, a zero level and 27 negative levels) are achieved by a 3-stage system which uses only 3 asymmetrical DC sources (with amplitude of 1Vin, 2Vin and 3Vin) and 7 capacitors (self-balanced as multiples of 1Vin). MATLAB/SIMULINK simulation results and experimental tests are given to validate the performance of proposed circuit.


  1. Multi-level inverter
  2. Switched-capacitor
  3. Bipolar converter
  4. Asymmetrical
  5. Self-balancing



Fig (1) Three stage structure of the proposed inverter



 Fig (2) Waveform of the output voltage in (a) 50Hz and pure resistive load (b the inset graphs of voltage and current

Fig (3) waveform of the output voltage in 50Hz with resistive-inductive load

Fig (4) Capacitor’s voltage in 50Hz (a) middle stage (b) last stage


In this paper, a multilevel inverter based on combination of multiple DC sources and switched-capacitors is presented. Unlike traditional converters which used H-bridge cell to produce negative voltage that the switches should withstand maximum output AC voltage, the suggested structure has the ability of generating bipolar voltage (positive, zero and negative), inherently. Operating principle of the proposed SCMLI in charging and discharging is carried out. Also, evaluation of reliability has been done and because of high number of redundancy, there has been many alternative switching states which help the proposed structure operate correctly even in fault conditions. For confirming the superiority than others, a comprehensive comparison in case of number of devices and efficiency is carried out and shows that the proposed topology has better performance than others. For validating the performance, simulation and experimental results are brought under introduced offline PWM control method.


[1] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilevel converters arrives,” IEEE Trans. Ind. Electron. Mag., vol. 2, no. 2, pp. 28–39, June, 2008.

[2] M. Saeedifard, P. M. Barbosa and P. K. Steimer,”Operation and Control of a Hybrid seven Level Converter,” IEEE Trans. Power Electron., vol. 27, no.2, pp. 652–660, February, 2012.

[3] A. Nami. “A New Multilevel Converter Configuration for High Power High Quality Application,” PhD Thesis, Queensland University of Technology, 2010.

[4] V. Dargahi, A. K. Sadigh, M. Abarzadeh, S. Eskandari and K. Corzine, “A new family of modular multilevel converter based on modified flying capacitor multicell converters IEEE Trans. Power Electron., vol. 30, no.

1, pp. 138-147, January, 2015.

[5] I. López, S. Ceballos, J. Pou, J. Zaragoza, J. Andreu, I. Kortabarria and V. G. Agelidis,” Modulation strategy for multiphase Neutral-Point Clamped converters,” IEEE Trans. Power Electron., vol. 31, no. 2, pp. 928–941, March, 2015.

Multi-Input Switched-Capacitor Multilevel Inverter for High-Frequency AC Power Distribution


This paper proposes a switched-capacitor multilevel inverter for high frequency AC power distribution systems. The proposed topology produces a staircase waveform with higher number of output levels employing fewer components compared to several existing switched capacitor multilevel inverters in the literature. This topology is beneficial where asymmetric DC voltage sources are available e.g. in case of renewable energy farms based AC microgrids and modern electric vehicles. Utilizing the available DC sources as inputs for a single inverter solves the major problem of connecting several inverters in parallel. Additionally, the need to stack voltage sources, like batteries or super-capacitors, in series which demand charge equalization algorithms, are eliminated as the voltage  sources employed share a common ground. The inverter inherently solves the problem of capacitor voltage balancing as each capacitor is charged to the value equal to one of input voltage every cycle. State analysis, losses and the selection of capacitance are examined. Simulation and experimental results at different distribution frequencies, power levels and output harmonic content are provided to demonstrate the feasibility of the proposed multilevel inverter topology.


  1. H-bridge
  2. HFAC power distribution
  3. High frequency DC/AC Inverter
  4. Multilevel inverter
  5. Selective harmonic elimination
  6. Switched-capacitor



Fig. 1: Proposed 7 level SCMLI topology


Fig. 2: Simulation waveforms at 400 Hz including nonidealities : (a) output voltage and current (b) switched capacitor voltage and current


A novel SCMLI topology for HFAC PDS has been proposed in this paper. The topology is applicable where unequal DC input sources are at disposal. Such scenarios are common in large renewable energy farms and electric vehicle networks. It is more convenient to employ multiple DC sources as input to a single inverter than to employ several inverters in parallel with their respective solitary DC input sources. This topology does not stack up the voltage sources in series and therefore does not require voltage balancing circuits. Since the switched capacitors employed copy the input voltage every cycle, the problem of voltage balancing has also been eliminated. The harmonic content in the waveform is analyzed and is found to be minimum. The proposed topology obtains higher number of voltage levels compared to several existing topologies. This paper utilizes the proposed topology for high frequency AC distribution. However, the same topology can be employed for 50 Hz / 60 Hz distribution by employing a larger switched capacitor. It is shown that the number of output voltage levels exponentially increase with increase in the employed input voltage sources and SCs. In the hardware results, it is shown that the 5th and 7th harmonics are minimized to very low value of 1V each. Results at different distribution frequencies and power levels are presented.


[1] Patel, Mukund R.,“High-Power High-Voltage Systems”, Spacecraft Power Systems, CRC press, 2004, ch. 22, sec. 22.7, pp. 539-543.

[2] Luk, Patrick Chi-Kwong, and Andy Seng Yim Ng. ”High Frequency AC Power Distribution Platforms.” Power Electronics in Smart Electrical Energy Networks. Springer London, 2008. pp. 175-201.

[3] Z. Ye, P. K. Jain and P. C. Sen, ”A Two-Stage Resonant Inverter With Control of the Phase Angle and Magnitude of the Output Voltage,” in IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2797-2812, Oct. 2007.

[4] J. A. Sabate, M. M. Jovanovic, F. C. Lee and R. T. Gean, ”Analysis and design-optimization of LCC resonant inverter for high-frequency AC distributed power system,” in IEEE Trans. Ind. Electron., vol. 42, no. 1,pp. 63-71, Feb 1995.

[5] Status of 20 kHz Space Station Power Distribution Technology, NASA Publication, TM 100781.

Transformer less Inverter with Virtual DC Bus Concept for Cost- Effective Grid-Connected PV Power Systems



In order to eliminate the common-mode (CM) leakage current in the transformer less photovoltaic (PV) systems, the concept of the virtual dc bus is proposed in this paper. By connecting the grid neutral line directly to the negative pole of the dc bus, the stray capacitance between the PV panels and the ground is bypassed. As a result, the CM ground leakage current can be suppressed completely. Meanwhile, the virtual dc bus is created to provide the negative voltage level for the negative ac grid current generation. Consequently, the required dc bus voltage is still the same as that of the full-bridge inverter. Based on this concept, a novel transformer less inverter topology is derived, in which the virtual dc bus is realized with the switched capacitor technology. It consists of only five power switches, two capacitors, and a single filter inductor. Therefore, the power electronics cost can be curtailed. This advanced topology can be modulated with the uni polar sinusoidal pulse width modulation (SPWM) and the double frequency SPWM to reduce the output current ripple. As a result, a smaller filter inductor can be used to reduce the size and magnetic losses. The advantageous circuit performances of the proposed transformer less topology are analyzed in detail, with the results verified by a 500-W prototype.


  1. Common mode (CM) current
  2. Photovoltaic (PV) system
  3. Switched capacitor
  4. Transformer less inverter
  5. Unipolar sinusoidal pulse width modulation (SPWM)
  6. Virtual dc bus.



Fig.1 Proposed topology


 Fig.2 Output current and grid voltage

Fig.3 Current harmonics distribution

Fig.4 Simulation waveform for reactive power generation

Fig.5 Enlarged figure for current stress on S3

Fig.6 CM current of H5 circuit

Fig.7 Current stress under different capacitor ratio for proposed circuit: (a) C1/C2=1/2; (b) C1/C2=2/1


The concept of the virtual DC bus is proposed to solve the CM current problem for the transformerless grid-connected PV inverter. By connecting the negative pole of the DC bus directly to the grid neutral line, the voltage on the stray PV capacitor is clamped to zero. This eliminates the CM current completely. Meanwhile, a virtual DC bus is created to provide the negative voltage level. The required DC voltage is only half of the half bridge solution, while the performance in eliminating the CM current is better than the full bridge based inverters. Based on this idea, a novel inverter topology is proposed with the virtual DC bus concept by adopting the switched capacitor technology. It consists of only five power switches and a single filter inductor. The proposed topology is especially suitable for the small power single phase applications, where the output current is relatively small so that the extra current stress caused by the switched capacitor does not cause serious reliability problem for the power devices and capacitors. With excellent performance in eliminating the CM current, the virtual DC bus concept provides a promising solution for the transformerless grid-connected PV inverters.


[1] Benner, J.P.; Kazmerski, L.; , “Photovoltaics gaining greater visibility,” Spectrum, IEEE , vol.36, no.9, pp.34-42, Sep 1999

[2] Zheng Zhao; Ming Xu; Qiaoliang Chen; Jih-Sheng Lai; Younghoon Cho; , “Derivation of boost-buck converter based high-efficiency robust PV inverter,” Energy Conversion Congress and Exposition (ECCE), 2010 IEEE , vol., no., pp.1479-1484, 12-16 Sept. 2010

[3] Erickson, R.W.; Rogers, A.P.; , “A Microinverter for Building-Integrated Photovoltaics,” Applied Power Electronics Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual IEEE , vol., no., pp.911-917, 15-19 Feb. 2009

[4] Kjaer, S.B.; Pedersen, J.K.; Blaabjerg, F.; , “A review of single-phase grid-connected inverters for photovoltaic modules,” Industry Applications, IEEE Transactions on , vol.41, no.5, pp. 1292- 1306, Sept.-Oct. 2005

[5] Koutroulis, E.; Blaabjerg, F.; , “Design optimization of grid-connected PV inverters,” Applied Power Electronics Conference and Exposition (APEC), 2011 Twenty-Sixth Annual IEEE , vol., no., pp.691-698, 6-11 March 2011

A New Cascaded Switched-Capacitor Multilevel Inverter Based on Improved Series-Parallel Conversion with Less Number of Components


The aim of this study is to present a new structure for switched-capacitor multilevel inverters (SCMLIs) which can generate a great number of voltage levels with optimum number of components for both symmetric and asymmetric value of dc voltage sources. Proposed topology consists of a new switched-capacitor dc/dc converter (SCC) which has boost ability and can charge capacitors as self-balancing by using proposed binary asymmetrical algorithm and series-parallel conversion of power supply. Proposed SCC unit is used in new configuration as a sub-multilevel inverter (SMLI) and then, these proposed SMLIs are cascaded together and create a new cascaded multilevel inverter topology which is able to increase the number of output voltage levels remarkably without using any full H-bridge cell and also can pass the reverse current for inductive loads. In this case, two half bridges modules besides two additional switches are employed in each of SMLI units instead of using a full H-bridge cell which contribute to reduce the number of involved components in the current path, value of blocked voltage, the variety of isolated dc voltage sources and as a result the overall cost by less number of switches in comparison with other presented topologies. The validity of the proposed SCMLI has been carried out by several simulation and experimental results.


  1. Cascade sub-multilevel inverter
  2. Series-parallel conversion
  3. Self-charge balancing
  4. Switched-capacitor




Fig. 1. Proposed 17-level structure



  • (a)
  • image003
  • (b)

Fig. 2. Steady states output voltage and current waveforms (a) in simulation Fig. 12. Transient states of output waveforms in simulation (b) in experiment ( 250V/div& 2A/div)


Fig. 3. Transient states of output waveforms in simulation

  • image005
  •                                                                                             (a)                                   (b)

Fig. 4. Harmonic orders (a) output voltage (b) output current in simulation


Fig. 5. Observed output voltage waveform at no-load condition (250V/div)







Fig. 6. Capacitors’ voltage ripple waveforms for first case study (a) in simulation (b) in experiment (25 V/dev&50V/div)









Fig. 7. Blocked voltage waveforms across switches of S1 (25V/div), S2 (100V/div), T1 (50V/div), T2 and T3 (100V/div) from left to right in the experiment



image017     (b)

Fig. 8. Output voltage and current waveforms for (a) inductive load in experiment (250 V/div & 2 A/div) (b) sudden step load in simulation







Fig. 9. Observed capacitors’ current (a) in simulation (b) in experiment (2A/div)


Fig. 10. (a) laboratory prototype (b) Output 49-level voltage and current waveforms in the experiment (250V/div & 2A/div)





Fig. 11. Across voltage waveforms of capacitors in upper and lower stages of SCCs in proposed 49-level inverter (a) v C 1 lower stage (5V/div) (b) v C 2 lower stage (10V/div) (c) v C 1 upper stage(25V/div) (d) v C 2 upper stage(50V/div)



In this paper, at the first, a new reduced components SCC topology was presented which has boost capability remarkably and also can pass the reverse current for inductive loads through existing power switches. The voltage of all capacitors in this structure is balanced by binary asymmetrical algorithm. Next, a new sub-multilevel structure based on suggested SCC was proposed which can generate all of the voltage levels at the output (even and odd). In this case, the conventional output H-bridge cell used to convert the polarity of SCC units, has been removed, therefore number of required IGBTs and other involved components, are decreased. After that, an optimizing  operation was presented which could obvious the number of required capacitors in each of SCC units that participate in the cascade sub-multilevel inverter (CSMLI) to generate maximum number of output voltage levels with less number of elements. Moreover comprehensive comparisons were given which prove the differences between improved symmetric and asymmetric CSMLIs in contrast to some of recently presented topologies in variety aspects. Finally, to confirm the performance and effectiveness of proposed CSMLI, several simulation and experimental results have been presented.


[1] J. Chavarria, D. Biel, F. Guinjoan, C. Meza, and J. J. Negroni, “Energy balance control of PV cascaded multilevel grid-connected inverters under level-shifted and phase-shifted PWMs,” IEEE Trans. Ind. Electron. vol. 60, no. 1, pp. 98–111, Jan. 2013.

[2] G. Buticchi, E. Lorenzani, and G. Franceschini, “A five-level single-phase grid-connected converter for renewable distributed systems,” IEEE Trans. Ind. Electron., vol. 60, no. 3, pp. 906–918, Mar. 2013.

[3] J. Rodriguez, L. J.Sheng, and P. Fang Zheng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.

[4] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilevel converters arrives,” IEEE Trans. Industrial Electronic Magazine, vol. 2, no. 2, pp. 28–39, Jun. 2008.

[5] M. M. Renge and H. M. Suryawanshi, “Five-Level Diode Clamped Inverter to Eliminate Common Mode Voltage and Reduce dv/dt in Medium Voltage Rating Induction Motor Drives,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1598-1607, Jul. 2008.


A Novel High StepUp DC DC Converter Based on Integrating Coupled Inductor and Switched-Capacitor Techniques for Renewable Energy Applications


In this paper, a novel high development up dc/dc converter is shown for maintainable power source applications. The proposed structure involves a coupled inductor and two voltage multiplier cells, in order to get high development up voltage gain. Likewise, two capacitors are charged in the midst of the kill time frame, using the essentialness set away in the coupled inductor which manufactures the voltage trade gain. The essentialness set away in the spillage inductance is reused with the use of a dormant fasten circuit. The voltage load on the basic power switch is furthermore diminished in the proposed topology. Thusly, a key influence switch with low resistance RDS(ON) can be used to diminish the conduction incidents. The action rule and the tireless state examinations are discussed inside and out. To check the execution of the showed converter, a 300-W lab demonstrate circuit is completed. The results affirm the speculative examinations and the practicability of the showed high development up converter.



Fig. 1. Circuit configuration of the presented high-step-up converter.


 image018 image019 image020 image021 image022 image023 image024

Fig. 2. Simulation results under load 300 W.


This paper demonstrates another high-advance up dc/dc converter for maintainable power source applications. The suggested converter is fitting for DG systems reliant on practical power sources, which require high-advance up voltage trade gain. The essentialness set away in the spillage inductance is reused to upgrade the execution of the showed converter. In addition, voltage load on the essential power switch is diminished. In like manner, a switch with a low on-state obstacle can be picked. The continuing state errand of the converter has been dismembered in detail. Moreover, the limit condition has been procured. Finally, a hardware show is executed which changes over the 40-V input voltage into 400-V yield voltage. The results exhibit the credibility of the presented converter.