A New Cascaded Switched-Capacitor Multilevel Inverter Based on Improved Series-Parallel Conversion with Less Number of Components


The aim of this study is to present a new structure for switched-capacitor multilevel inverters (SCMLIs) which can produce a great number of voltage levels with optimum number of components for both symmetric and asymmetric value of dc voltage sources.


planned topology consists of a new switched-capacitor dc/dc converter (SCC) which has boost ability and can charge capacitors as self-balancing by using planned binary asymmetrical algorithm and series-parallel conversion of power supply.


planned SCC unit is used in new configuration as a sub-multilevel inverter (SMLI) and then, these planned SMLIs are cascaded together and create a new cascaded multilevel inverter topology which is able to increase the number of output voltage levels remarkably without using any full H-bridge cell and also can pass the reverse current for inductive loads.


In this case, two half bridges modules besides two additional switches are employed in each of SMLI units instead of using a full H-bridge cell which contribute to reduce the number of involved components in the current path, value of blocked voltage, the variety of isolated


dc voltage sources and as a result the overall cost by less number of switches in comparison with other presented topologies. The validity of the planned SCMLI has been carried out by several simulation and experimental results.


  1. Cascade sub-multilevel inverter
  2. Series-parallel conversion
  3. Self-charge balancing
  4. Switched-capacitor




Fig. 1. Proposed 17-level structure



    • (a)
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  • (b)

Fig. 2. Steady states output voltage and current waveforms (a) in simulation Fig. 12. Transient states of output waveforms in simulation (b) in experiment ( 250V/div& 2A/div)


Fig. 3. Transient states of output waveforms in simulation

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  •                                                                                             (a)                                   (b)

Fig. 4. Harmonic orders (a) output voltage (b) output current in simulation


Fig. 5. Observed output voltage waveform at no-load condition (250V/div)







Fig. 6. Capacitors’ voltage ripple waveforms for first case study (a) in simulation (b) in experiment (25 V/dev&50V/div)







Fig. 7. Blocked voltage waveforms across switches of S1 (25V/div), S2 (100V/div), T1 (50V/div), T2 and T3 (100V/div) from left to right in the experiment



image017     (b)

Fig. 8. Output voltage and current waveforms for (a) inductive load in experiment (250 V/div & 2 A/div) (b) sudden step load in simulation







Fig. 9. Observed capacitors’ current (a) in simulation (b) in experiment (2A/div)


Fig. 10. (a) laboratory prototype (b) Output 49-level voltage and current waveforms in the experiment (250V/div & 2A/div)





Fig. 11. Across voltage waveforms of capacitors in upper and lower stages of SCCs in proposed 49-level inverter (a) v C 1 lower stage (5V/div) (b) v C 2 lower stage (10V/div) (c) v C 1 upper stage(25V/div) (d) v C 2 upper stage(50V/div)


In this paper, at the first, a new reduced element SCC topology was given which has boost capability remarkably and also can pass the reverse current for inductive loads through existing power switches. The voltage of all capacitors in this structure is balanced by binary asymmetrical algorithm.


Next, a new sub-multilevel structure based on suggested SCC was planned which can generate all of the voltage levels at the output (even and odd). In this case, the normal output H-bridge cell used to convert the polarity of SCC units, has been removed, therefore number of needed IGBTs and other involved components, are decreased.


After that, an optimizing  operation was given which could obvious the number of needed capacitors in each of SCC units that participate in the cascade sub-multilevel inverter (CSMLI) to generate maximum number of output voltage levels with less number of elements. Moreover broad connection were given which prove


the differences between improve symmetric and asymmetric CSMLIs in contrast to some of recently given topologies in variety aspects. Finally, to confirm the work and efficiency of planned CSMLI, several simulation and experimental results have been presented.


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A Switched-Capacitor Inverter Using Series/Parallel Conversion with Inductive Load


A new switched-capacitor inverter is prepared. The prepared inverter outputs larger voltage than the input voltage by change the capacitors in series and in parallel. The highest output voltage is driven by the number of the capacitors. The prepared inverter, which does not need any inductors, can be smaller than a normal two-stage unit which happen of a boost converter and an inverter bridge.


Its output frequency are decreased compared to a normal voltage source single phase full bridge inverter. In this paper, the circuit configuration, the logical operation, the simulation results with MATLAB/ SIMULINK, and the experimental results are shown. The experimental results give with the logical calculation and the simulation results.


  1. Charge pump
  2. Multicarrier PWM
  3. Multilevel Inverter
  4. Switched capacitor (SC)



Fig. 1. Circuit topology of the switched-capacitor inverter using series/ parallel conversion.




Fig. 2. Simulated voltage waveforms of the proposed inverter (n = 2) designed for high power at 4.50 [kW], switching frequency f = 40 [kHz] and reference waveform frequency fref = 1 [kHz]. (a) Bus voltage waveform vbus and (b) the output voltage waveform vout.


Fig. 3. Simulated current waveforms of the capacitor iC1 in the proposed inverter (n = 2).(a) Designed for low power at 5.76 [W] and (b) designed for high power at 4.50 [kW].


Fig. 4. Simulated spectra of the bus voltage waveform of the proposed inverters (n = 2) normalized with the fundamental component. (a) Designed for low power at 5.76 [W] and (b) designed for high power at 4.50 [kW].


Fig. 5. Simulated bus voltage waveforms vbus and the voltage waveforms of the load resistance vR of the proposed inverter (n = 2) designed for low power at 5.76 [W] with an inductive load.


In this paper, a novel boost change-capacitor inverter was prepared. The circuit topology was produce. The modulation method, the decision method of the capacitance, and the loss calculation of the proposed inverter were shown. The circuit operation of the proposed inverter was proved by the simulation results and the experimental results with a resistant load and an inductive load.


The prepared inverter outputs a larger voltage than the input voltage by change the capacitors in series and in parallel. The inverter can operate with an inductive load. The structure of the inverter is simpler than the normal change-capacitor inverters. THD of the output waveform of the inverter is reduce compared to the normal single phase full bridge inverter as the normal multilevel inverter.


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