Commutation Torque Ripple Reduction in BLDC Motor Using Modified SEPIC Converter and Three-level NPC Inverter

ABSTRACT:

This paper presents a new power converter topology to suppress the torque ripple due to the phase current commutation of a brushless DC motor (BLDCM) drive system. A combination of a 3-level diode clamped multilevel inverter (3-level DCMLI), a modified single-ended primary-inductor converter (SEPIC), and a dc-bus voltage selector circuit are employed in the proposed torque ripple suppression circuit. For efficient suppression of torque pulsation, the dc-bus voltage selector circuit is used to apply the regulated dc-bus voltage from the modified SEPIC converter during the commutation interval. In order to further mitigate the torque ripple pulsation, the 3-level DCMLI is used in the proposed circuit. Finally, simulation and experimental results show that the proposed topology is an attractive option to reduce the commutation torque ripple significantly at low and high speed applications.

KEYWORDS:

  1. Brushless direct current motor (BLDCM)
  2. Dc-bus voltage control
  3. Modified single-ended primary-inductor converter
  4. 3-level diode clamped multilevel inverter (3-level DCMLI)
  5. Torque ripple

 SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM:

Fig. 1. Proposed converter topology with a dc-bus voltage selector circuit for BLDCM

 EXPECTED SIMULATION RESULTS:

 

 Fig. 2. Simulated waveforms of phase current and torque at 1000 rpm and 0.825 Nm with 5 kHz switching frequency. (a) BLDCM fed by 2-level inverter. (b) BLDCM fed by 3-level DCMLI. (c) BLDCM fed by 2-level inverter with SEPIC converter and a switch selection circuit. (d) BLDCM fed by proposed topology.

Fig. 3. Simulated waveforms of phase current and torque at 6000 rpm and 0.825 Nm with 5 kHz switching frequency. (a) BLDCM fed by 2-level inverter. (b) BLDCM fed by 3-level DCMLI. (c) BLDCM fed by 2-level inverter with SEPIC converter and a switch selection circuit. (d) BLDCM fed by proposed topology.

Fig. 4. Simulated waveforms of phase current and torque at 1000 rpm and 0.825 Nm with 20 kHz switching frequency. (a) BLDCM fed by 2-level inverter. (b) BLDCM fed by 3-level DCMLI. (c) BLDCM fed by 2-level inverter with SEPIC converter and switch a selection circuit. (d) BLDCM fed by proposed topology.

Fig. 5. Simulated waveforms of phase current and torque at 6000 rpm and 0.825 Nm with 20 kHz switching frequency. (a) BLDCM fed by 2-level inverter. (b) BLDCM fed by 3-level DCMLI. (c) BLDCM fed by 2-level inverter with SEPIC converter and a switch selection circuit. (d) BLDCM fed by proposed topology.

Fig. 6. Simulated waveforms of phase current and torque at 1000 rpm and 0.825 Nm with 80 kHz switching frequency. (a) BLDCM fed by 2-level inverter. (b) BLDCM fed by 3-level DCMLI. (c) BLDCM fed by 2-level inverter with SEPIC converter and a switch selection circuit. (d) BLDCM fed by proposed topology.

Fig. 7. Simulated waveforms of phase current and torque at 6000 rpm and 0.825 Nm with 80 kHz switching frequency. (a) BLDCM fed by 2-level inverter. (b) BLDCM fed by 3-level DCMLI. (c) BLDCM fed by 2-level inverter with SEPIC converter and a switch selection circuit. (d) BLDCM fed by proposed topology.

CONCLUSION:

In this paper, a commutation torque ripple reduction circuit has been proposed using 3-level DCMLI with modified SEPIC converter and a dc-bus voltage selector circuit. A laboratory-built drive system has been tested to verify the proposed converter topology. The suggested dc-bus voltage control strategy is more effective in torque ripple reduction in the commutation interval. The proposed topology accomplishes the successful reduction of torque ripple in the commutation period and experimental results are presented to compare the performance of the proposed control technique with the conventional 2-level inverter, 3-level DCMLI, 2-level inverter with SEPIC converter and the switch selection circuit-fed BLDCM. In order to obtain significant torque ripple suppression, quietness and higher efficiency, 3-level DCMLI with modified SEPIC converter and the voltage selector circuit is a most suitable choice to obtain high-performance operation of BLDCM. The proposed topology may be used for the torque ripple suppression of BLDCM with the very low stator winding inductance.

REFERENCES:

[1] N. Milivojevic, M. Krishnamurthy, Y. Gurkaynak, A. Sathyan, Y.-J. Lee, and A. Emadi, “Stability analysis of FPGA-based control of brushless DC motors and generators using digital PWM technique,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 343–351, Jan. 2012.

[2] X. Huang, A. Goodman, C. Gerada, Y. Fang, and Q. Lu, “A single sided matrix converter drive for a brushless dc motor in aerospace applications,” IEEE Trans. Ind. Electron., vol. 59, no. 9, pp. 3542–3552, Sep. 2012.

[3] X. Huang, A. Goodman, C. Gerada, Y. Fang, and Q. Lu, “Design of a five-phase brushless DC motor for a safety critical aerospace application,” IEEE Trans. Ind. Electron., vol. 59, no. 9, pp. 3532-3541, Sep. 2012.

[4] J.-G. Lee, C.-S. ark, J.-J. Lee, G. H. Lee, H.-I. Cho, and J.-P. Hong, “Characteristic analysis of brushless motor condering drive type,” KIEE, pp. 589-591, Jul. 2002.

Comprehensive Study of Single-Phase AC-DC Power Factor Corrected Converters with High-Frequency Isolation

ABSTRACT: Solid-state switch mode AC-DC converters having high-frequency transformer isolation are developed in buck, boost, and buck-boost configurations with improved power quality in terms of reduced total harmonic distortion (THD) of input current, power-factor correction (PFC) at AC mains and precisely regulated and isolated DC output voltage feeding to loads from few Watts to several kW. This paper presents a comprehensive study on state of art of power factor corrected single-phase AC-DC converters configurations, control strategies, selection of components and design considerations, performance evaluation, power quality considerations, selection criteria and potential applications, latest trends, and future developments. Simulation results as well as comparative performance are presented and discussed for most of the proposed topologies.

 

INDEX TERMS: AC-DC converters, harmonic reduction, high-frequency (HF) transformer isolation, improved power quality converters, power-factor correction.

 

SOFTWARE: MATLAB/SIMULINK

image001

Fig. 1. Classification of improved power quality single-phase AC-DC converters with HF transformer isolation.

CIRCUIT CONFIGURATIONS

A. Buck AC-DC Converters

image002         image003

Fig. 2. Buck forward AC-DC converter with voltage follower control.

Fig. 3. Buck push-pull AC-DC converter with voltage follower control.

                                           image004       image005

 

 

 

 

Fig. 4. Half-bridge buck AC-DC converter with voltage follower control.

Fig. 5. Buck full-bridge AC-DC converter with voltage follower control

 B. Boost AC-DC Converters

image006     image007

Fig. 6. Boost forward AC-DC converter with current multiplier control.

Fig. 7. Boost push-pull AC-DC converter with current multiplier control.

image008     image009

Fig. 8. Boost half-bridge AC-DC converter with current multiplier control.

Fig. 9. Boost full-bridge AC-DC converter with current multiplier control.

 C. Buck-Boost AC-DC Converters

image010           image011

Fig. 10. Flyback AC-DC converter with current multiplier control.

Fig. 11. Cuk AC-DC converter with voltage follower control.

image012      image013

Fig. 12. SEPIC AC-DC converter with voltage follower control.

Fig. 13. Zeta AC-DC converter with voltage follower control.

 

SIMULATION RESULTS:

image014

Fig. 14. Current waveforms and its THD for buck AC-DC converter topologies in CCM. (a) Forward buck topology (Fig. 2).( b) Push-pull buck topology (Fig. 3). (c) Half-bridge buck topology (Fig. 4). (d) Bridge buck topology (Fig. 5).

image015

Fig. 15. Current waveforms and its THD for boost AC-DC converter topologies in CCM. (a) Forward boost topology (Fig. 6). (b) Push-pull boost topology (Fig. 7). (c) Half-bridge boost topology (Fig. 8). (d) Bridge boost topology (Fig. 9).

image016

Fig. 16. Current waveforms and its THD for buck-boost AC-DC converter topologies in CCM. (a) Flyback topology (Fig. 10). (b) Cuk topology (Fig. 11). (c) SEPIC topology (Fig. 12). (d) Zeta topology (Fig. 13).

image017

Fig. 17. Current waveforms and its THD for buck AC-DC converter topologies in DCM. (a) Forward buck topology (Fig. 2). (b) Push-pull buck topology (Fig. 3). (c) Half-bridge buck topology (Fig. 4). (d) Bridge buck topology (Fig. 5).

image018

Fig. 18. Current waveforms and its THD for boost AC-DC converter topologies in DCM. (a) Forward boost topology (Fig. 6). (b) Push-pull boost topology (Fig. 7).

image019

Fig. 19. Current waveforms and its THD for buck-boost AC-DC converter topologies in DCM. (a) Flyback topology (Fig. 10). (b) Cuk topology (Fig. 11). (c) SEPIC topology (Fig. 12). (d) Zeta topology (Fig. 13).

 

CONCLUSION

A comprehensive review of the improved power quality HF transformer isolated AC-DC converters has been made to present a detailed exposure on their various topologies and its design to the application engineers, manufacturers, users and researchers. A detailed classification of these AC-DC converters into 12 categories with number of circuits and concepts has been carried out to provide easy selection of proper topology for a specific application. These AC-DC converters provide a high level of power quality at AC mains and well regulated, ripple free isolated DC outputs. Moreover, these converters have been found to operate very satisfactorily with very wide AC mains voltage and frequency variations resulting in a concept of universal input. The new developments in device technology, integrated magnetic and microelectronics are expected to provide a tremendous boost for these AC-DC converters in exploring number of additional applications. It is hoped that this exhaustive design and simulation of these HF transformer isolated AC-DC converters is expected to be a timely reference to manufacturers, designers, researchers, and application engineers working in the area of power supplies.

 

REFERENCES

[1] IEEE Recommended Practices and Requirements for Harmonics Control in Electric Power Systems, IEEE Standard 519, 1992.

[2] Electromagnetic Compatibility (EMC) – Part 3: Limits- Section 2: Limits for Harmonic Current Emissions (equipment input current 􀀀16 A per phase), IEC1000-3-2 Document, 1st ed., 1995.

[3] A. I. Pressman, Switching Power Supply Design, 2nd ed. New York: McGraw-Hill, 1998.

[4] K. Billings, Switchmode Power Supply Handbook, 2nd ed. NewYork: McGraw-Hill, 1999.

[5] N. Mohan, T. Udeland, and W. Robbins, Power Electronics: Converters, Applications and Design, 3rd ed. New York: Wiley, 2002.