A Novel Multilevel Inverter Based on Switched DC Sources

ABSTRACT:  

This paper presents a multilevel invert er that has been conceptualized to reduce component count, particularly for a large number of output levels. It comprises floating input dc sources alternately connected in opposite polarities with one another through power switches whereas each input dc level appears in the stepped load voltage either individually or in additive combinations with other input levels. This approach results in reduced number of power switches as compared to classical to p o log i e s. A single-phase five-level invert er demonstrates the working principle of the proposed topology. The simulation investigates the topology and an exhaustive comparison of the proposed topology is made against the classical cascaded H-bridge topology.

 SOFTWARE: MAT LAB/SIM U LINK

 CIRCUIT DIAGRAM:

 

Fig. 1. Single-phase invert er based on the proposed topology with two input sources.

 EXPECTED SIMULATION RESULTS:

 

 Fig. 2. (a) Reference and carrier wave forms for the proposed scheme for a five-level output. (b) Aggregated signal “a(t).”

Fig. 3. Switching pulse pattern for the five-level invert er.

Fig. 4. Simulation results. (a) Five-level voltage output. (b) Harmonic spectrum of the load voltage.

Fig. 5. Simulation results. (a) Load current waveform with an R L load (R =

2 Ω and L = 2 m H). (b) Harmonic spectrum of the load current.

 

CONCLUSION:

As M LI s are gaining interest, efforts are being directed toward reducing the device count for increased number of output levels, therefore A novel topology for M LI s has been proposed in this paper to reduce the device count. The working principle of the proposed topology has been explained, and mathematical formulations corresponding to output voltage, source currents, voltage stresses on switches, and power losses have been developed. Simulation studies performed on a five-level invert er based on the proposed structure have been validated experimentally.

Comparison

Comparison of the proposed topology with conventional top o l o g i es reveals that the proposed topology significantly reduces the number of power switches and associated gate driver circuits. Analytical comparisons on the basis of losses and switch cost indicate that the proposed topology is highly competitive. The proposed topology can be effectively employed for applications where isolated dc sources are available. The advantage of the reduction in the device count, however, imposes two limitations: 1) requirement of isolated dc sources as is the case with the C H B topology and 2) curtailed modular it y  and fault-tolerant capabilities as compared to the C H B topology.

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