Grid Voltages Estimation for Three-Phase PWM Rectifiers Control Without AC Voltage Sensors

ABSTRACT

This paper proposes another AC voltage sensorless control plot for three-stage beat width tweak rectifier. Another startup procedure to guarantee a smooth beginning of the framework is likewise proposed. The sensorless control conspire utilizes a versatile neural (AN) estimator embedded in voltage-arranged control to dispense with the matrix voltage sensors. The built up AN estimator joins a versatile neural system in arrangement with a versatile neural channel. The AN estimator structure prompts straightforward, precise and quick network voltages estimation, and makes it perfect for ease advanced flag processor execution. Lyapunov based security and parameters tuning of the AN estimator are performed. Reproduction and trial tests are completed to confirm the plausibility and adequacy of the AN estimator. Acquired outcomes demonstrate that; the proposed AN estimator exhibited quicker union and preferred exactness over the second request summed up integrator based estimator; the new startup technique maintained a strategic distance from the over-current and diminished the settling time; the AN estimator introduced superior exhibitions even under contorted and unequal matrix voltages.

 

BLOCK DIAGRAM:

Fig. 1. Overall structure of the developed AC voltage sensorless control.

EXPECTED SIMULATION RESULTS

Fig. 2. Steady-state performances of the AN estimator in diode rectifier operation mode (experiment): (a) computed input voltages vαn and vβn, (b) actual AC-line currents iα and iβ, (c) actual grid voltage eα, estimated grid voltage eα,est and estimation error and (d) actual grid voltage eβ, estimated grid voltage eβ,est and estimation error.

Fig. 3. Steady-state performances of the PLL in diode rectifier operation mode (experiment): (a) computed dq components (ed, eq) with actual grid  voltages and computed dq components (ed,est, eq,est) with estimated grid  voltages and (b) computed angles θ and θest with actual and estimated grid voltages, respectively.

Fig. 4. Performances of the AN estimator at startup (experiment): (a) input voltages vαn and vβn, (b) actual AC-line currents iα and iβ, (c) reference and  measured DC-link voltages (Vdc ref, Vdc), (d) actual grid voltage eα, estimated  grid voltage eα,est and estimation error and (d) actual grid voltage eβ, estimated grid voltage eβ,est and estimation error.

Fig. 5. Performances of the PLL at startup (experiment): (a) computed dq components (ed, eq) with actual grid voltages and computed dq components (ed,est, eq,est) with estimated grid voltages and (b) computed angles θ and θest with actual and estimated grid voltages, respectively.

Fig. 6. Transient performances of the AN estimator under Vdc ref step change (experiment): (a) actual grid voltage eα, estimated grid voltage eα,est and estimation error, (b) actual grid voltage eβ, estimated grid voltage eβ,est and estimation error, (c) actual AC-line currents iα and iβ and (d) reference and measured DC-link voltages.

Fig. 7. Transient performances of the PLL under Vdc ref step change (experiment): (a) computed dq components (ed, eq) with actual grid voltages and computed dq components (ed,est, eq,est) with estimated grid voltages and (b) computed angles θ and θest with actual and estimated grid voltages, respectively.

 

Fig. 8. Transient performances of the AN estimator under load resistance variation (experiment): (a) actual grid voltage eα, estimated grid voltage eα,est and estimation error, (b) actual grid voltage eβ, estimated grid voltage eβ,est and estimation error and (c) actual AC-line currents.

Fig. 9. Transient performances of the PLL under load resistance variation (experiment): (a) computed dq components (ed, eq) with actual grid voltages and computed dq components (ed,est, eq,est) with estimated grid voltages and (b) computed angles θ and θest with actual and estimated grid voltages, respectively.

 

Fig. 10. Transient performances of the AN estimator under symmetric grid voltages sag (experiment): (a) actual grid voltage eα, estimated grid voltage eα,est and estimation error and (b) actual grid voltage eβ, estimated grid voltage eβ,est and estimation error and (c) actual AC-line currents.

Fig. 11. Transient performances of the PLL under symmetric grid voltages sag (experiment): (a) computed dq components (ed, eq) with actual grid voltages and computed dq components (ed,est, eq,est) with estimated grid voltages and (b) computed angles θ and θest with actual and estimated grid voltages, respectively.

 

Fig. 12. Transient performances of the AN estimator under grid voltages unbalance (experiment): (a) actual grid voltage eα, estimated grid voltage eα,est and estimation error and (b) actual grid voltage eβ, estimated grid voltage eβ,est and estimation error and (c) actual AC-line currents.

Fig. 13. Transient performances of the PLL under grid voltages unbalance (experiment): computed dq components (ed, eq) with actual grid voltages and computed dq components (ed,est, eq,est) with estimated grid voltages and (b) computed angles θ and θest with actual and estimated grid voltages, respectively.

Fig. 14. Transient performances of the AN estimator under distorted grid voltages (simulation): (a) actual grid voltage eα and estimated grid voltage eα,est, (b) actual grid voltage eβ and estimated grid voltage eβ,est and (c) actual AC-line currents.

Fig. 15. Transient performances of the PLL under distorted grid voltages (simulation): computed dq components (ed, eq) with actual grid voltages and computed dq components (ed,est, eq,est) with estimated grid voltages and (b) computed angles θ and θest with actual and estimated grid voltages respectively.

CONCLUSION

In this work, another AN estimator for killing the lattice voltage sensors in VOC of three-stage PWM rectifier has been proposed. The built up AN estimator joins estimation ability of the ANN and sifting property of the ANF. Lyapunov’s hypothesis based soundness investigation has been misused for ideal tuning of the AN estimator. Thus, basic, exact and quick framework voltages estimation has been gotten. To keep away from current overshoot and to lessen the settling time at the startup, another startup procedure has been proposed to instate the VOC. The adequacy of the proposed technique has been tentatively illustrated. A correlation between the proposed AN estimator and the as of late created SOGI based estimator has been directed. This examination has unmistakably shown quicker union and better exactness of the proposed estimator. At long last, power of the AN estimator in regards to step change in DC-interface voltage reference, stack obstruction variety and non-perfect lattice voltages conditions (symmetrical hang, unbalance, bending) has been researched through reproduction and test tests. The acquired outcomes have exhibited superior exhibitions of the proposed AN estimator inside the examined working conditions.

 

Simulation Analysis of DVR Performance for Voltage Sag Mitigation

ABSTRACT:

Voltage sag is truly one of intensity quality issue and it end up extreme to mechanical clients. Voltage hang can cause miss task to a few touchy electronic types of gear. That issue can be moderating with voltage infusion strategy utilizing custom power gadget, Dynamic Voltage Restorer (DVR). This paper presents displaying and investigation of a DVR with heartbeat width tweak (PWM) based controller utilizing Matlab/Simulink. The execution of the DVR relies upon the effectiveness of the control strategy associated with exchanging the inverter. This paper proposed two control procedures which is PI Controller (PI) and Fuzzy Logic Controller (FL). Complete outcomes are introduced to evaluate the execution of every controller as the best power quality arrangement. Different components that likewise can influence the execution and ability of DVR are displayed also.

 

 BLOCK DIAGRAM:

 Figure1. DVR Modelling using Matlab/Simulink

 EXPECTED SIMULATION RESULTS:

Figure 2. (a) Injection voltage from DVR controlled by PI ; (b) injection voltage controlled by FL

Figure 3. (a) Output voltage at load 1 after injection voltage from DVR controlled by PI; (b) Output voltage at load 1after injection voltage controlled by FL.

Figure 4. (a) Injection voltage from DVR controlled by PI; (b) injection voltage controlled by FL.

Figure 5. (a) Output voltage at load 1 after injection voltage from DVR controlled by PI; (b) Output voltage at load 1after injection voltage controlled by FL.

Figure 6. THD generated when PI controller is applied

Figure 7. THD generated when FL controller is applied.

CONCLUSION:

In this examination, the displaying and reenactment of DVR controlled by PI and FL Controller has been produced utilizing Matlab/Simulink. For both controller, the reenactment result demonstrates that the DVR repays the hang rapidly (70μs) and gives great voltage direction. DVR handles numerous types, adjusted and unequal blame with no troubles and infuses the proper voltage segment to address any blame circumstance happened in the supply voltage to keep the heap voltage adjusted and steady at the ostensible esteem. The two controllers demonstrate an incredible execution and create low THD (<5%). Notwithstanding, it very well may be seen that FL Controller gives better execution with THD produced with just 0.64% while PI created 1.68% THD. In any case, other a few factors that can influence the execution of DVR should be tended to for improvement of the yield voltage. These variables are the vitality stockpiling limit and transformer rating. From the recreation, it unmistakably demonstrates the significance of these two factors and how they influence the execution of DVR. Hence, with regards to usage, it is urgent to think about these elements, so the execution of DVR is enhanced.

Thermal Stresses Relief Carrier-Based PWM Strategy for Single Phase Multilevel Inverters

ABSTRACT

Enhancing power cycling capability of power semiconductor devices is highly demanded in order to increase the long term reliability of multilevel inverters. Ageing of power switches and their cooling systems leads to their accelerated damage due to excess power losses and junction temperatures. Therefore, thermal stresses relief (TSR) is the most effective solution for lifetime extension of power semiconductor devices. This paper presents a new thermal stresses relief carrier-based pulse width modulation (TSRPWM) strategy for extending the lifetime of semiconductor switches in single-phase multilevel inverters. The proposed strategy benefits the inherent redundancy among switching states in multilevel inverters to optimally relieve the thermally stressed device. The proposed algorithm maintains the inverter operation without increased stresses on healthy switches and without reduction of the output power ratings. In addition, the proposed algorithm preserves voltage balance of the DC-link capacitors. The proposed strategy is validated on single phase five level T-type inverter system with considering different locations of thermal stresses detection. Experimental prototype of the selected case study is built to verify the results. Moreover, comparisons with the most featured strategies in literature are given in detail.

KEYWORDS

  1. Lifetime extension
  2. long term reliability
  3. multilevel inverter
  4. pulse width modulation (PWM)
  5. thermal stresses relief

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

 Fig. 1. A schematic diagram of PWM controlled full bridge n-level T-type inverter

EXPECTED SIMULATION RESULTS

 Fig. 2. Simulation results of the proposed strategy at TSD in SA11 at mi=0.85.

 

 Fig. 3. Simulation results of the proposed strategy at TSD in SA11 at mi=0.45.

Fig. 4. Simulation results of the proposed TSRPWM strategy at TSD in SA12 and mi=0.85.

CONCLUSION

This paper has proposed a new carrier-based modulation strategy, called TSRPWM, for single phase multilevel inverters. It retains the same benefits as the conventional carrier PWM methods, i.e., a simple and easy implementation, but presents a significantly reduced power losses and thermal stresses of the stressed semiconductor devices. The main idea of the new proposed strategy is adaptively selecting the redundant switching states in each switching cycle, in order to optimize power losses through the thermally-stressed device. Therefore, both of the junction temperature and temperature cycling of the stressed device are reduced by the proposed strategy compared with normal mode operation of the device. The results of simulation and experimental prototypes are conformed and verified the new proposed concept. A generalized implementation of the proposed TSRPWM, to provide thermal stresses relief for any of the components and for any n-level inverters, is also presented. Moreover, the proposed strategy maintains the inverter operation with the same output ratings, and voltage balance over DC-link capacitors. Finally, the performance of the proposed strategy is compared with the prominent strategies in literature, and the distinction of the proposed strategy has become clear.

REFERENCES

[1] Shaoyong Yang, A. Bryant, P. Mawby, Dawei Xiang, Li Ran, and P. Tavner, “An industry-based survey of reliability in power electronic converters,” IEEE Trans. Ind. Appl., vol. 47, no. 3, pp. 1441–1451, May 2011.

[2] S. E. De Leon-Aldaco, H. Calleja, and J. Aguayo Alquicira, “Reliability and mission profiles of photovoltaic systems: a FIDES approach,” IEEE Trans. Power Electron., vol. 30, no. 5, pp. 2578–2586, May 2015.

[3] B. Ji, X. Song, E. Sciberras, W. Cao, Y. Hu,0 and V. Pickert, “Multiobjective design optimization of IGBT power modules considering power cycling and thermal cycling,” IEEE Trans. Power Electron., vol. 30, no. 5, pp. 2493–2504, May 2015.

[4] U.-M. Choi, F. Blaabjerg, and K.-B. Lee, “Study and handling methods of power IGBT module failures in power electronic converter systems,” IEEE Trans. Power Electron., vol. 30, no. 5, pp. 2517–2533, May 2015.

[5] P. A. Mawby, W. Lai, H. Qin, O. Alatise, S. Xu, M. Chen, and L. Ran, “Study on the lifetime characteristics of power modules under power cycling conditions,” IET Power Electron., vol. 9, no. 5, pp. 1045–1052, Apr. 2016.

A Seven-Switch Five-Level Active-Neutral-Point-Clamped Converter and Its Optimal Modulation Strategy

ABSTRACT:

Multilevel inverters are receiving more attentions nowadays as one of preferred solutions for medium and high power applications. As one of the most popular hybrid multilevel inverter topologies, the Five-Level Active-Neutral-Point-Clamped inverter (5L-ANPC) combines the features of the conventional Flying-Capacitor (FC) type and Neutral-Point-Clamped (NPC) type inverter and was commercially used for industrial applications. In order to further decrease the number of active switches, this paper proposes a Seven-Switch 5L-ANPC (7S-5L-ANPC) topology, which employs only seven active switches and two discrete diodes. The analysis has shown a lower current rating can be selected for the seventh switch under high power factor condition, which is verified by simulation results. The modulation strategy for 7S-5L-ANPC inverter is discussed. A 1KVA single-phase experimental prototype is built to verify the validity and flexibility of the proposed topology and modulation method.

KEYWORDS:

  1. Multilevel inverter
  2. Active-Neutral-Point-Clamped (ANPC) inverter
  3. Flying-Capacitor
  4. Pulse-Width-Modulation (PWM)

 SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

 

Fig.1 (a) Proposed topology.

 EXPECTED SIMULATION RESULTS

 

 Fig. 2. Simulation results under unity power factor condition. (a) Output voltage and FC voltage. (b) T7 current in case 1. (c) T7 current in case 2. (d) T7 current in case 3. (e) T7 current in case 4.

Fig. 3. Simulation results under reactive power condition (PF = 0.9, capacitive). (a) Output voltage and FC voltage. (b) T7 current in case 1. (c) T7 current in case 2. (d) T7 current in case 3. (e) T7 current in case 4

Fig. 4. Simulation results under reactive power condition (PF = 0). (a) Output voltage and FC voltage. (b) T7 current in case 1. (c) T7 current in case 2. (d) T7 current in case 3. (e) T7 current in case 4.

Fig. 5. Experimental results under unity power factor condition: waveforms of inverter output voltage, grid voltage, FC voltage and output current.

CONCLUSION:

In this paper, a novel 7S-5L-ANPC inverter topology has been proposed. As compared with the conventional 5L-ANPC inverter, it requires seven active switches for single phase and a low current rating switch can be selected for the seventh switch under high power factor situation. The operating principles and switching states are presented. The detailed comparison between the proposed topology and the conventional 5L-ANPC topologies in terms of voltage stress and efficiency is made. The specific modulation strategy of 7S-5L-ANPC inverter under reactive power operation has been proposed. Computer simulation and experimental prototype based on a single phase 1KVA prototype have been carried out in unity power factor condition and reactive power condition. The validity and advantages of the proposed topology and modulation method are demonstrated.

REFERENCES:

[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. W. Bin Wu, J. Rodriguez, M. a. Pérez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[2] F. Z. Peng, W. Qian, and D. Cao, “Recent advances in multilevel converter / inverter topologies and applications,” in Proc. IPEC, 2010, pp. 492–501.

[3] F. Z. Peng, “A generalized multilevel inverter topology with self voltage balancing,” IEEE Trans. Ind. Electron., vol. 37, no. 2, pp. 611–618, Feb. 2001.

[4] J. Rodriguez, Jih-Sheng Lai, and Fang Zheng Peng, “Multilevel inverters: a survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Apr. 2002.

[5] L. M. Tolbert, “A Multilevel Modular Capacitor Clamped DC-DC Converter,” in Proc. 41st IAS, 2006, pp. 966–973.

High-performance multilevel inverter drive of brushless DC Motor

ABSTRACT:

The brushless DC (BLDC) motor has numerous applications in high-power systems; it is simple in construction, is cheap, requires less maintenance, has higher efficiency, and has high power in the output unit. The BLDC motor is driven by an inverter. This paper presents design and simulation for a three-phase three-level inverter to drive the BLDC motor. The multilevel inverter is driven by discrete three-phase pulse width modulation (DPWM) generator that forced-commuted the IGBT’s three-level converters using three bridges to vectored outputs 12- pulses with three levels. Using DPWM with a three-level inverter solves the problem of harmonic distortions and low electromagnetic interference. This topology can attract attention in high-power and high-performance voltage applications. It provides a three-phase voltage source with amplitude, phase, and frequency that are controllable. The proposed model is used with the PID controller to follow the reference speed signal designed by variable steps. The system design is simulated by using Matlab/Simulink. Satisfactory results and high performance of the control with steady state and transient response are obtained. The results of the proposed model are compared with the variable DC-link control. The results of the proposed model are more stable and reliable.

KEYWORDS:

  1. Brushless DC Motor
  2. Multilevel Inverter
  3. High-Performance Drive
  4. Pulse Width Modulation (PWM)
  5. Maltlab
  6. Simulink

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Figure 1. BLDC motor with MLI driven with PID controller.

EXPECTED SIMULATION RESULTS:

 

 Figure. 2. Output of three-phase three-level inverter with DPWM.

Figure 3. The sample from output of the DPWM

Figure 4. Analysis of response for the proposed MLI with PID controller of BLDC motor.

Fig. 5. Two outputs of controllers with proposed MLI and variable DC-link

CONCLUSION:

The proposed MLI performance analysis was successfully presented by using Matlab/Simulink software. The proposed topology can be easily extended to a higher-level inverter. The simulation results were sine waves and exhibited fewer ripples and low losses. This system would show its feasibility in practice. The vector control was described in adequate detail and was implemented with a three-level MLI. This method enabled the operation of the drive at zero direct axis stator current. Transient results were obtained when a DPWM was started from a standstill to a required speed. The performance of the vector control in achieving a fast reversal of PDPWM even at very high speed ranges is quite satisfactory. The performance of the proposed three-phase MLI was investigated and was found to be quite satisfactory. A comparison was made between the PID controller–based proposed model MLI and the controller with variable DC-link voltage. The results showed that the proposed model responded better in transient and steady states and was more reliability with high performance.

REFERENCES:

[1] P. D. Kiran, M. Ramachandra, “Two-Level and Five-Level Inverter Fed BLDC Motor Drives”, International Journal of Electrical and Electronics Engineering Research, Vol. 3, Issue 3, pp 71-82, Aug 2013

[2] N. Karthika, A. Sangari, R. Umamaheswari , “Performance Analysis of Multi Level Inverter with DC Link Switches for Renewable Energy Resources”, International Journal of Innovative Technology and Exploring Engineering, Volume-2, Issue-6, pp 171-176, May 2013

[3] A. Jalilvand R. Noroozian M. Darabian, “Modeling and Control Of Multi-Level Inverter for Three-Phase Grid-Connected Photovoltaic Sources”, International Journal on Technical and Physical Problems of Engineering, Iss. 15, Vol. 5, No.2, pp 35-43, June 2013

[4] P. Karuppanan, K. Mahapatra, “PI, PID and Fuzzy Logic Controlled Cascaded Voltage Source Inverter Based Active Filter For Power Line Conditioners”, Wseas Transactions On Power Systems, Issue 4, Volume 6, pp 100-109, October 2011

[5] D. Balakrishnan, D. Shanmugam, K.Indiradevi, “Modified Multilevel Inverter Topology for Grid Connected PV Systems”, American Journal of Engineering Research, Vol. 02, Iss.10, pp-378-384, 2013