Power Quality Enhancement in Residential Smart Grids through Power Factor Correction Stages

Power Quality Enhancement titles

ABSTRACT:

The proliferation of non-linear loads and the increasing penetration of Distributed Energy Resources (D ER) in Medium-Voltage (M V) and Low-Voltage (L V) distribution grids, make it more difficult to maintain the power quality levels in residential electrical grids, especially in the case of weak grids. Most household appliances contain a conventional Power Factor Corrector (PFC) rectifier, which maximizes the load Power Factor (PF) but does not contribute to the regulation of the voltage Total Harmonic Distortion (TH D V ) in residential electrical grids.

This

manuscript proposes a modification for PFC controllers by adapting the operation mode depending on the measured TH D V . As a result, the PF Cs operate either in a low current Total Harmonic Distortion (TH DI ) mode or in the conventional resistor emulator mode and contribute to the regulation of the TH D V and the PF at the distribution feeders. To prove the concept, the modification is applied to a current sensor less Non-Linear Controller (N LC) applied to a single-phase Boost rectifier. Experimental results show its performance in a PFC front-end stage operating in Continuous Conduction Mode (CC M) connected to the grid with different TH D V.

BLOCK DIAGRAM:

 

 Fig. 1. Residential L V grid with household appliances feed through conventional AC/DC stages (without the proposed operation mode selector) and the proposed P Q E controller.

 EXPECTED SIMULATION RESULTS:

 

Fig. 2. Experimental results of P Q E PFC at 50 Hz. Voltage and current wave forms in a) resistor emulator mode (k = 0), b) sinusoidal current mode (k = 1) and c) measured spectra in both operation modes.

Fig. 3. Experimental results of  P Q E PFC at 60 Hz. Voltage and current wave forms in a) resistor emulator mode (k = 0), b) sinusoidal current mode (k = 1) and c) measured spectra in both operation modes.

Fig. 4. Experimental results of P Q E PFC at 400 Hz. Voltage and current wave forms in a) resistor emulator mode (k = 0), b) sinusoidal current mode (k = 1) and c) measured spectra in both operation modes.

CONCLUSION:

The consequence on the electrical power quality of connecting household appliances to the grid through PFC stages has been assessed considering different TH D V scenarios. As has been shown in (17) and (23), there are conditions under which sinusoidal current consumption results in better PF at the PC C than with resistor emulator behavior, commonly assumed to be ideal for PFC stages. A modification of the carrier signal of N LC controllers applied to PFC stages is designed to impress sinusoidal input current despite the input voltage distortion. The line current estimation with no interaction with the power stage implements the N LC with high noise immunity. The digital implementation of the non-linear controller is appropriate to define the carrier and to include additional reduction of the current distortion depending on the application.

P Q E controller

The P Q E controller can be applied to mitigate the effect of nonlinear loads within household appliances on residential electrical grids. The operation mode of the digital controller can be autonomously adjusted through the locally measured TH D V , without extra circuitry. The user or a TH D V threshold detection selects the convenient behavior (either resistor emulator or pure sinusoidal current). Experimental results obtained with high TH D V (above 5 %) confirm the feasibility of the P Q E controller in both sinusoidal current and resist i v e emulator modes.

REFERENCES:

[1] IEEE Std. 519-2014 (Revision of IEEE Std. 519-1992), IEEE Recommended Practice and Requirements for Harmonic Control in Electric Power Systems, D OI 10.1109/IEEE STD.2014.6826459, pp. 1–29, Jun. 2014.

[2] Y. J. Wang, R. M. O’Connell, and G. Brownfield, “Modeling and prediction of distribution system voltage distortion caused by nonlinear residential loads,” IEEE Trans. Power Del., vol. 16, D OI 10.1109/61.956765, no. 4, pp. 744–751, Oct. 2001.

[3] H. Ora e e, “A quantitative approach to estimate the life expectancy of motor insulation systems,” IEEE Trans. Die l e ct r. Elect r. In s u l., vol. 7, D OI 10.1109/94.891990, no. 6, pp. 790–796, Dec. 2000.

[4] D. Fab i an i and G. C. Mont an a r i, “The effect of voltage distortion on ageing acceleration of insulation systems under partial discharge activity,” IEEE Elect r. Ins u l. Mag., vol. 17, D OI 10.1109/57.925300, no. 3, pp. 24–33, May. 2001.

[5] T. J. Dion i s e and V. Lo r ch, “Harmonic filter analysis and redesign for a modern steel facility with two melt furnaces using dedicated capacitor banks,” in IEEE I AS Annual Meeting, vol. 1, D OI 10.1109/I AS.2006.256496, pp. 137–143, Oct. 2006.

Novel High Efficiency High Voltage Gain Topologies for AC-DC Conversion with Power Factor Correction for Elevator Systems

ABSTRACT:

This paper proposed Novel power factor corrected ac dc rectifier typologies suitable for induction motor drive based elevator application. These converters make use of coupled induct or for power conversion and are capable of providing high voltage gain at low duty cycle and high efficiency. Feedback control loop controls the current flowing through the coupled induct or to achieve unity power factor. The TH D value of the current i approximately 4.8 % which is within the limits prescribed by various standards.

With

the use of coupled induct or, the voltage stress of the switches operating at high frequency is reduced, which reduces switching losses. The loss comparison with the conventional converters shows a reduction of at least 22 % of losses. The proposed scheme also results in reduction of the variable frequency drive’s dc link capacitance value.  As an ultra capacitor bank is interfaced with the dc link through a bidirectional converter for improving efficiency and providing transient power requirements. This also helps in increasing the reliability and dynamic response of the system. The settling time for a step change in voltage reference is reduced by nearly 50%. MAT LAB/Sim u link simulations validates the proposed typologies and schemes.

BLOCK DIAGRAM:

 Fig. 1 Block diagram of an elevator system

 EXPECTED SIMULATION RESULTS:

 Fig. 2(a) Input current and voltage of the proposed 1 p h rectifier system with PFC; (b)3 p h current for PFC operation of proposed rectifier configuration; (c) The dc link voltage step changes for 10μF and 500μF dc link capacitor; and (d) Ultra capacitor current.

CONCLUSION:

Simulation studies proposed, analyzed and validated the Novel AC DC PW M rectifier typologies for 1 p h and 3 p h systems, based on high voltage gain dc dc converter principle. A major advantage of these typologies is that it is possible to achieve higher voltage gain at lower duty ratio. This paper maintained operation symmetry  and achieved the Input power factor correction. The use of coupled induct or s enhances gain, but it also increases the ripple in the input current as there is an increase in turns ratio. Thus, there is a trade off between the achievable gain and the ripple.

comparison

The losses of the proposed converter are compared with the conventional ac dc converter, and observed the reduction of about 22% losses. The losses estimated through experimental studies also reduced from 29 W to 24 W with the use  of proposed topology . This shows a reduction of 17% losses in experiments. Therefore, the proposed converter gives higher efficiency than the conventional ac-dc converters. And the use of an auxiliary storage reduced the dc link capacitance value from 500 μF to 10 μF for a 1 p h system. For the 3 p h system, the auxiliary unit is used as a support during the grid voltage sag condition thereby reducing the dc link capacitance requirement. A low value of dc link capacitance not only helps in reducing the size. And improving the reliability of system, also in improving the dynamic response of the system.

results

The paper presented the simulation results of the complete system . A detailed description of the thought process behind the development of the proposed converter is also presented. The same thought process is extended to the development of such converter typologies. The voltage stress on switch S 2 and S 3 reduces to 1 and 8th of its value as compared to the conventional topology. But, the value of peak current increases ‘n’ times. The increase in peak current increases the high frequency current ripple in the input side. However, the increase in the value of ‘n’ decreases the duty cycle. Therefore, increased the overall efficiency of the converter.

This

paper proposed the unidirectional ac dc typologies. But, they can be made bidirectional by connecting a controllable switch across the diodes. This scheme is useful for the scenarios where the loads are regenerating. These bidirectional typologies are used as dc ac converters to feed power into the grid. Thus, giving very wide and relevant scope of the proposed schemes.

 

REFERENCES:

[1] Ash o k B. K u l k a r n i, H e in Nguyen, E. W. Ga u d e t, “A Comparative Evaluation of Line Regenerative and Non- regenerative Vector Controlled Drives for AC Gear less Elevators” 35th I AS Annual Meeting and World Conference on Industrial Applications of Electrical Energy, Rome, Italy: Institute of Electrical and Electronics Engineers Inc., Pis cat away, NJ, Oct 2000, vol. 3.pp 1431 to 1437.

[2] “IEEE Std. 519”, IEEE Recommended Practices and Requirements for Harmonic Control in Electric Power Systems, 1992.

[3] “IE C 1000 3 2 Int. Std.”, Limits for Harmonics Current Emissions (Equipment Input Cur rent 16 A per Phase), 1995.

[4] “IE C 61000 3 4”, Limitations of Emission of Harmonic Current in Low- Voltage Power Supply Systems for Equipment with Rated Current Greater than 16 A, 1998.

[5] J. Hahn, P. N. En jet i and I. J. Pit e l, “A new three-phase power-factor correction (PFC) scheme using two single-phase PFC modules,” in IEEE Transactions on Industry Applications, vol. 38, no. 1, pp. 123-130, Jan/Feb 2002.

References

[6]Hen g ch u n Mao, C. Y. Lee, D. B o r o ye vi ch and S. Hit i, “Review of high performance three-phase power-factor correction circuits,” in IEEE
Transactions on Industrial Electronics, vol. 44, no. 4, pp. 437-446, Aug 1997.
[7] Y u n g ta e k Jan g and M. M. Jo v a n o v i c, “A comparative study of singles witch three-phase high-power-factor rectifiers,” IEEE Transactions on Industry Applications, vol. 34, no. 6, pp. 1327-1334, Nov/Dec 1998.
[8] M. M. Cameron, “Trends in power factor correction with harmonic filtering,” in IEEE Transactions on Industry Applications, vol. 29, no. 1, pp. 60-65, Jan/Feb 1993.
[9] C. L. Cooper, R. O. Pr  a g ale and T. J. Di o n i s e, “A Systematic Approach for Medium-Voltage Power Factor Correction Design,” IEEE Transactions on Industry Applications, vol. 49, no. 3, pp. 1043-1055, May-June 2013.

Critical Current Control (C3) and Modeling of a Buck Based LED Driver with Power Factor Correction

ABSTRACT

Buck converter has a good aptitude for LED driver application. Here a new technique introduced to control and model a buck converter in the closed loop condition using Lagrange equation. To improve the final model accuracy, parasitic elements of the converter are taken into account. The main advantage of this method is its novelty and simple implementation. Also, the converter power factor has improved under critical current control (C3) technique. Frequency response and step response of the small signal model are derived and analysed. The theoretical predictions are tested and validated by means of PSIM software. Finally, precise agreement between the proposed model and the simulation results has obtained.

 

INDEX TERMS:

  1. Power factor correction
  2. LED driver
  3. Buck converter
  4. Small signal model.
  5. critical current

 

SOFTWARE: MATLAB/SIMULINK

  

CIRCUIT DIAGRAM

critical current control

Fig. 1. Converter overall circuitry by C3 method in the PFC mode

 

SIMULATION RESULTS

Fig. 2. Converter source current and voltage along with each other

Fig. 3. Reference current, input voltage and current after the bridge

Fig.4. Harmonic contents of the converter input current

Fig.5. Output voltage at the start-up moment

Fig.6. Output capacitor current

Fig.7. Load change effect on the converter input current

CONCLUSION

This paper analyses a buck based LED driver with improved power factor. Power factor correction is done using critical current control (C3) or borderline conduction mode (BCM). Also, the Lagrange differential equations are employed here as an efficient tool for switching converter modeling in the closed loop condition. The proposed modeling technique gives the designer better intuition about the circuit under study rather than traditional state space averaging (SSA) method. SSA is a tedious and fully mathematical tool for switching converters modeling. In addition, parasitic elements of the converter have taken into account so it helps to select the circuit parts value correctly before manufacturing process. Dynamic behaviour of the converter is analysed in both frequency and time domain such as transfer functions and step response. A PI compensator is employed in the closed feedback loop to stabilize and modulate the reference current amplitude corresponding to the demanded power. Since this method relying on the averaging method, then the final model is reliable from 0 Hz up to half of switching frequency according to the Nyquist theorem. Finally, the simulation results confirm the proposed model exactness and indicate the rapidity of system step response under compelling conditions.

 

REFERENCES

  • Jardini J.A. et al., Power Flow Control in the Converters Interconnecting AC-DC Meshed Systems, Przegląd Elektrotechniczny, 01(2015), 46-49.
  • Gajowik T., Rafał K., Bobrowska M., Bi-directional DC-DC converter in three-phase Dual Active Bridge Topology, Przegląd Elektrotechniczny, 05(2014), 14-20.
  • Kazmierczuk M.K., Pulse Width Modulated DC-DC Power Converters, Wiley, Ohio, 2008.
  • Ben-Yaakov S., Average simulation of PWM converters by direct implementation of behavioural relationships, IEEE Conf. , APEC, 1993, San diego, CA., 510-516.
  • Shepherd W., Zhang L., Power Converter Circuits, Marcel & Dekker Inc., New York, 2004.

Power Factor Correction in Bridgeless-Luo Converter Fed BLDC Motor Drive

IEEE Transactions on Industry Applications, 2013

ABSTRACT:

This paper presents a power factor correction (PFC) based bridgeless-Luo (BL-Luo) converter fed brushless DC (BLDC) motor drive. A single voltage sensor is used for the speed control of BLDC motor and PFC at AC mains. The voltage follower control is used for a BL-Luo converter operating in discontinuous inductor current mode (DICM). The speed of the BLDC motor is controlled by an approach of variable DC link voltage, which allows a low frequency switching of voltage source inverter (VSI) for electronic commutation of BLDC motor; thus offers reduced switching losses. The proposed BLDC motor drive is designed to operate over a wide range of speed control with an improved power quality at AC mains. The power quality indices thus obtained are under the recommended limits of IEC 61000-3-2. The performance of the proposed drive is validated with test results obtained on a developed prototype of the drive.

KEYWORDS:

  1. Bridgeless Luo Converter
  2. Brushless DC motor
  3. Power Factor Correction
  4. Power Quality
  5. Voltage Source Inverter

 SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Proposed PFC BL-Luo Converter fed BLDC motor drive.

EXPECTED SIMULATION RESULTS:

 

 Fig. 2. Test results of proposed BLDC motor drive (a) At rated load  torque on BLDC motor with Vdc=50V and Vs=220V, (b) At rated load torque on BLDC motor with Vdc=200V and Vs=220V

Fig. 3. Test results of proposed BLDC motor drive showing (a) iLi1, iLo1, VC1 with Vs, (b) PFC converter’s switch voltage and current at rated load torque on BLDC motor (c) Enlarged waveforms of PFC converter’s switch voltage and current.

Fig. 4. Test results of proposed BLDC motor drive showing dynamic performance (a) during starting at 50V, (b) during change in DC link voltage from 100V to 150V, (c) during change in supply voltage from 250 to 180V.

CONCLUSION:

A Power Factor Correction based BL-Luo converter fed BLDC motor drive has been proposed for wide range of speeds and supply voltages. A single voltage sensor based speed control of BLDC motor using a concept of variable DC link voltage has been used. The PFC BL-Luo converter has been designed to operate in DICM and to act as an inherent power factor preregulator. An electronic commutation of the BLDC motor has been used which utilizes a low frequency operation of VSI for reduced switching losses. The proposed BLDC motor drive has been designed and its performance is simulated in MATLAB/Simulink environment for achieving an improved power quality over wide range of speed control. Finally, the performance of proposed drive has been verified experimentally on a developed hardware prototype. A satisfactory performance of proposed drive has been achieved and is a recommended solution for low power applications.

REFERENCES:

[1] C. L. Xia, Permanent Magnet Brushless DC Motor Drives and Controls, Wiley Press, Beijing, 2012.

[2] T. Kenjo and S. Nagamori, Permanent Magnet Brushless DC Motors, Clarendon Press, Oxford, 1985.

[3] R. Krishnan, Electric Motor Drives: Modeling, Analysis and Control, Pearson Education, India, 2001.

[4] T. J Sokira and W. Jaffe, Brushless DC Motors: Electronic Commutation and Control, Tab Books, USA, 1989.

[5] H. A. Toliyat and S. Campbell, DSP-based Electromechanical Motion Control, CRC Press, New York, 2004.

power factor correction

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A Unity Power Factor Bridgeless Isolated Cuk Converter Fed Brushless-DC Motor Drive

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2013

ABSTRACT: This work presents a power factor correction (PFC) based bridgeless isolated Cuk converter fed brushless DC (BLDC) motor drive. A variable DC link voltage of the voltage source inverter (VSI) feeding BLDC motor is used for its speed control. This allows the operation of VSI in fundamental frequency switching (FFS) to achieve an electronic commutation of BLDC motor for reduced switching losses. A bridgeless configuration of an isolated Cuk converter is derived for elimination of front end diode bridge rectifier (DBR) to reduce conduction losses in it. The proposed PFC based bridgeless isolated Cuk converter is designed to operate in discontinuous inductor current mode (DICM) to achieve an inherent PFC at AC mains. The proposed drive is controlled using a single voltage sensor to develop a cost effective solution. The proposed drive is implemented to achieve a unity power factor at AC mains for a wide range of speed control and supply voltages. An improved power quality is achieved at AC mains with power quality indices within limits of IEC 61000-3-2 standard.

KEYWORDS:

  1. BLDC Motor
  2. Bridgeless Isolated Cuk Converter
  3. Discontinuous Inductor Current Mode
  4. Power Factor Correction
  5. Power Quality
  6. Voltage Source Inverter

 SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Proposed configuration of a bridgeless isolated Cuk converter feeding BLDC motor drive.

EXPECTED SIMULATION RESULTS:
DC link voltage

Fig. 2. Test results of the proposed drive during its operation at rated loading condition with DC link voltage as (a) 130 V and (b) 50 V.

Fig. 3. Test results of the proposed drive during its operation at rated condition showing (a) input inductor currents (b) output inductors current and (c) HFT currents.

Fig. 4. Test results of the proposed drive during its operation at rated condition showing intermediate capacitors voltages (a) VC11 and VC12 and (b) VC21 and VC22.

 

Fig. 5. (a) Test results of the proposed drive during its operation at rated condition showing (a) voltage and current stress on PFC converter switches and (b) its enlarged waveforms.

Fig. 6. Test results of the proposed drive during (a) starting at DC link voltage of 50V, (b) speed control corresponding to change in DC link voltage fro 50V to 100V and (c) supply voltage fluctuation from 250V to 200V.

 

CONCLUSION:

A new configuration of bridgeless isolated-Cuk converter fed BLDC motor drive has been proposed for low power household appliances. The speed control of BLDC motor has been achieved by controlling the DC link voltage of VSI feeding BLDC motor. This has facilitated the operation of VSI in low frequency switching mode for reducing the switching losses associated with it. This bridgeless isolated-Cuk converter has been designed for the elimination of diode bridge rectifier at the front-end for reducing the conduction losses in the front-end converter. This PFC converter has been operated in DICM for DC link voltage control and inherent power factor correction is achieved at the AC mains. A prototype of proposed drive has been implemented using a DSP. Satisfactory test results for proposed bridgeless isolated- Cuk-converter fed BLDC motor has been evaluated for its operation over complete speed range. Moreover, the performance of proposed drive is also evaluated for operation at wide range of supply voltages. The obtained power quality indices have been found within the limits of power quality standards such as IEC 61000-3-2.

REFERENCES:

[1] C. L. Xia, Permanent Magnet Brushless DC Motor Drives and Controls Wiley Press, Beijing, 2012.

[2] Y. Chen, C. Chiu, Y. Jhang, Z. Tang and R. Liang, “A Driver for the Single-Phase Brushless DC Fan Motor with Hybrid Winding Structure,” IEEE Trans. Ind. Electron., vol. 60, no. 10, pp. 4369

[3] X. Huang, A. Goodman, C. Gerada, Y. Fang and Q. L Matrix Converter Drive for a Brushless DC Motor in Aerospace Applications,” IEEE Trans. Ind. Elect., Sept. 2012.

[4] J. Moreno, M. E. Ortuzar and J. W. Dixon, “Energy for a hybrid electric vehicle, using ultra capacitors and neural networks,” IEEE Trans. Ind. Electron., vol.53, no.2, pp. 614

[5] P. Pillay and R. Krishnan, “Modeling of permanent magnet motor drives,” IEEE Trans. Ind. Elect.vol.35, no.4, pp. 537-541, Nov 1988.

Isolated Cuk Converter projects list

Comprehensive Study of Single-Phase AC-DC Power Factor Corrected Converters with High-Frequency Isolation

ABSTRACT: Solid-state switch mode AC-DC converters having high-frequency transformer isolation are developed in buck, boost, and buck-boost configurations with improved power quality in terms of reduced total harmonic distortion (THD) of input current, power-factor correction (PFC) at AC mains and precisely regulated and isolated DC output voltage feeding to loads from few Watts to several kW. This paper presents a comprehensive study on state of art of power factor corrected single-phase AC-DC converters configurations, control strategies, selection of components and design considerations, performance evaluation, power quality considerations, selection criteria and potential applications, latest trends, and future developments. Simulation results as well as comparative performance are presented and discussed for most of the proposed topologies.

 

INDEX TERMS: AC-DC converters, harmonic reduction, high-frequency (HF) transformer isolation, improved power quality converters, power-factor correction.

 

SOFTWARE: MATLAB/SIMULINK

image001

Fig. 1. Classification of improved power quality single-phase AC-DC converters with HF transformer isolation.

CIRCUIT CONFIGURATIONS

A. Buck AC-DC Converters

image002         image003

Fig. 2. Buck forward AC-DC converter with voltage follower control.

Fig. 3. Buck push-pull AC-DC converter with voltage follower control.

                                           image004       image005

 

 

 

 

Fig. 4. Half-bridge buck AC-DC converter with voltage follower control.

Fig. 5. Buck full-bridge AC-DC converter with voltage follower control

 B. Boost AC-DC Converters

image006     image007

Fig. 6. Boost forward AC-DC converter with current multiplier control.

Fig. 7. Boost push-pull AC-DC converter with current multiplier control.

image008     image009

Fig. 8. Boost half-bridge AC-DC converter with current multiplier control.

Fig. 9. Boost full-bridge AC-DC converter with current multiplier control.

 C. Buck-Boost AC-DC Converters

image010           image011

Fig. 10. Flyback AC-DC converter with current multiplier control.

Fig. 11. Cuk AC-DC converter with voltage follower control.

image012      image013

Fig. 12. SEPIC AC-DC converter with voltage follower control.

Fig. 13. Zeta AC-DC converter with voltage follower control.

 

SIMULATION RESULTS:

image014

Fig. 14. Current waveforms and its THD for buck AC-DC converter topologies in CCM. (a) Forward buck topology (Fig. 2).( b) Push-pull buck topology (Fig. 3). (c) Half-bridge buck topology (Fig. 4). (d) Bridge buck topology (Fig. 5).

image015

Fig. 15. Current waveforms and its THD for boost AC-DC converter topologies in CCM. (a) Forward boost topology (Fig. 6). (b) Push-pull boost topology (Fig. 7). (c) Half-bridge boost topology (Fig. 8). (d) Bridge boost topology (Fig. 9).

image016

Fig. 16. Current waveforms and its THD for buck-boost AC-DC converter topologies in CCM. (a) Flyback topology (Fig. 10). (b) Cuk topology (Fig. 11). (c) SEPIC topology (Fig. 12). (d) Zeta topology (Fig. 13).

image017

Fig. 17. Current waveforms and its THD for buck AC-DC converter topologies in DCM. (a) Forward buck topology (Fig. 2). (b) Push-pull buck topology (Fig. 3). (c) Half-bridge buck topology (Fig. 4). (d) Bridge buck topology (Fig. 5).

image018

Fig. 18. Current waveforms and its THD for boost AC-DC converter topologies in DCM. (a) Forward boost topology (Fig. 6). (b) Push-pull boost topology (Fig. 7).

image019

Fig. 19. Current waveforms and its THD for buck-boost AC-DC converter topologies in DCM. (a) Flyback topology (Fig. 10). (b) Cuk topology (Fig. 11). (c) SEPIC topology (Fig. 12). (d) Zeta topology (Fig. 13).

 

CONCLUSION

A comprehensive review of the improved power quality HF transformer isolated AC-DC converters has been made to present a detailed exposure on their various topologies and its design to the application engineers, manufacturers, users and researchers. A detailed classification of these AC-DC converters into 12 categories with number of circuits and concepts has been carried out to provide easy selection of proper topology for a specific application. These AC-DC converters provide a high level of power quality at AC mains and well regulated, ripple free isolated DC outputs. Moreover, these converters have been found to operate very satisfactorily with very wide AC mains voltage and frequency variations resulting in a concept of universal input. The new developments in device technology, integrated magnetic and microelectronics are expected to provide a tremendous boost for these AC-DC converters in exploring number of additional applications. It is hoped that this exhaustive design and simulation of these HF transformer isolated AC-DC converters is expected to be a timely reference to manufacturers, designers, researchers, and application engineers working in the area of power supplies.

 

REFERENCES

[1] IEEE Recommended Practices and Requirements for Harmonics Control in Electric Power Systems, IEEE Standard 519, 1992.

[2] Electromagnetic Compatibility (EMC) – Part 3: Limits- Section 2: Limits for Harmonic Current Emissions (equipment input current 􀀀16 A per phase), IEC1000-3-2 Document, 1st ed., 1995.

[3] A. I. Pressman, Switching Power Supply Design, 2nd ed. New York: McGraw-Hill, 1998.

[4] K. Billings, Switchmode Power Supply Handbook, 2nd ed. NewYork: McGraw-Hill, 1999.

[5] N. Mohan, T. Udeland, and W. Robbins, Power Electronics: Converters, Applications and Design, 3rd ed. New York: Wiley, 2002.

New AC-DC Power Factor Correction Architecture Suitable for High Frequency Operation

 

ABSTRACT:

 This paper presents a novel ac-dc power factor correction (PFC) power conversion architecture for single-phase grid interface. The proposed architecture has significant advantages for achieving high efficiency, good power factor, and converter miniaturization, especially in low-to-medium power applications. The architecture enables twice-line-frequency energy to be buffered at high voltage with a large voltage swing, enabling reduction in the energy buffer capacitor size, and elimination of electrolytic capacitors. While this architecture can be beneficial with a variety of converter topologies, it is especially suited for system miniaturization by enabling designs that operate at high frequency (HF, 3 – 30 MHz). Moreover, we introduce circuit implementations that provide efficient operation in this range. The proposed approach is demonstrated for an LED driver converter operating at a (variable) HF switching frequency (3 – 10 MHz) from 120Vac, and supplying a 35Vdc output at up to 30W. The prototype converter achieves high efficiency (92 %) and power factor (0.89), and maintains good performance over a wide load range. Owing to architecture and HF operation, the prototype achieves a high ‘box’ power density of 50W/ in3 (‘displacement’ power density of 130W/ in3), with miniaturized inductors, ceramic energy buffer capacitors, and a small-volume EMI filter.

KEYWORDS:

  1. AC-DC
  2. High frequency
  3. Buck
  4. Power factor correction PFC
  5. Power factor
  6. LED
  7. Electromagnetic interference EMI

 SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

 

image002

Fig. 1: The proposed grid interface power conversion architecture comprises a line-frequency rectifier, a stack of capacitors, a set of regulating converters, and a power combining converter.

EXPECTED SIMULATION RESULTS:

 image004Fig. 2: Operation of the prototype converter from a 120Vac line voltage to a 35Vdc output. Each figure illustrates voltage and / or current waveforms over the ac line cycle: (a) the measured 120Vac line input voltage and the measured voltages across the capacitor stack (output of the bridge rectifier) (b) the measured voltages across C1 and across C2 for a delivered output power of 29W (c) the measured input current waveform at 29W output power (d) the measured input current waveform at 20W output power (e) the output voltage waveform at 29W output power (f) the switched capacitor voltage waveform at 29W output power.

CONCLUSION:

A new single-phase grid interface ac-dc PFC architecture is introduced and experimentally demonstrated. In addition to enabling high efficiency and good power factor, this PFC architecture is particularly advantageous in that it enables extremely high operating frequencies (into the HF range) and reduction in energy buffer capacitor values, each of which contributes to converter miniaturization. The proposed stacked combined architecture significantly decreases the voltage stress of the active and passive devices and reduces characteristic impedance levels, enabling substantial increases in switching frequency when utilized with appropriate converter topologies. Moreover, good power factor is achieved while dynamically buffering twice-line-frequency ac energy with relatively small capacitors operating with large voltage swing. The prototype converter achieves high efficiency and good power factor over a wide power range, and meets the CISPR Class-B Conducted electromagnetic interference (EMI) Limits. The prototype converter based on the architecture and selected high-frequency circuit topology demonstrates an approximate factor of 10 reduction in volume compared to typical designs. The prototype has a very high ‘box’ power density of 50W=in3 (‘displacement’ power density of 130W=in3) with miniaturized inductors, a small volume of EMI filter, and ceramic energy buffer capacitors. Lastly, as described in the appendix, the proposed architecture can be realized in various ways (e.g., with alternative topologies) to realize features such as galvanic isolation and universal input range.

REFERENCES:

[1] O. Garcia, J. Cobos, R. Prieto, P. Alou, and J. Uceda, “Single phase power factor correction: a survey,” Power Electronics, IEEE Transactions on, vol. 18, no. 3, pp. 749–755, May 2003.

[2] G. Moschopoulos and P. Jain, “Single-phase single-stage power-factor corrected converter topologies,” Industrial Electronics, IEEE Transactions on, vol. 52, no. 1, pp. 23–35, Feb 2005.

[3] B. Singh, B. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. Kothari, “A review of single-phase improved power quality ac-dc converters,” Industrial Electronics, IEEE Transactions on, vol. 50, no. 5, pp. 962–981, Oct 2003.

[4] Energy Star, “Energy star program requirements for integral LED lamps,” Energy Star, Tech. Rep., Aug. 2010.

[5] ——, “Energy star program requirements for computers,” Energy Star, Tech. Rep., Jun. 2014.

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