Dynamic voltage restorer employing multilevel cascaded H-bridge inverter

IET Power Electronics, 2016

ABSTRACT: This study presents design and analysis of a dynamic voltage restorer (DVR) which employs a cascaded multilevel inverter with capacitors as energy sources. The multilevel inverter enables the DVR to connect directly to the medium voltage networks, hence, eliminating the series injection transformer. Using zero energy compensation method, the DVR does not need active energy storage systems, such as batteries. Since the energy storage system only includes capacitors, the control system will face some additional challenges compared with other DVR systems. Controlling the voltage of capacitors around a reference voltage and keeping the balance between them, in standby and compensation period, is one of them. A control scheme is presented in this study that overcomes the challenges. Additionally, a fast three-phase estimation method is employed to minimize the delay of DVR and to mitigate the voltage sags as fast as possible. Performance of the control scheme and estimation method is assessed using several simulations in MATLAB / SIMULINK environments.

KEYWORDS:

  1. Multilevel inverter
  2. cascaded H-bridge inverter
  3. Dynamic Voltage Restorer

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

 Multilevel inverter

 Fig. 1 DVR strcuctures  a) Conventional DVR b) CHB-based DVR

 EXPECTED SIMULATION RESULTS:

Fig. 2 Three-phase voltage sag a) Network voltage b) Injected voltage by the DVR c) Load-side voltage

 Fig. 3 Unbalanced voltage sag (a 20% voltage sag on phase A) a) Source voltage b) Injected voltage by the DVR c) Load-side voltage

Fig. 4 Voltages of the DC link capacitors

Fig. 5 Three-phase 20% voltage sag with voltage harmonics a) Network voltage b) Injected voltage by the DVR c) Load-side voltage

 

CONCLUSION:

This paper presented design and performance assessment of a DVR based on the voltage sag data collected from MWPI. Using a multilevel converter, the proposed DVR was capable of direct connection to the medium voltage-level network without a series injection transformer. In addition, development of zero active power compensation technique helps to achieve voltage restoration goal just by the capacitors as energy storages. Due to internal losses of H-bridge cells and probable inaccuracies in measurements, voltage of DC link capacitors may become unequal, which prevents proper operation of the converter. A voltage control scheme, comprised of three separate controllers, was proposed in this paper for keeping voltage balance among the DC link capacitors within nominal range. A fast estimation method was also employed for calculation of phase and magnitude terms in an unbalanced three-phase system. This estimation method is able to recognise voltage sags in approximately half a cycle. Several simulations were performed in PSCAD/EMTDC environment to verify the performance of CHB-based DVR. Additionally, a laboratory-scale prototype of the proposed DVR was built and tested. Results of the experimental test also confirmed validity of the proposed control system.

 REFERENCES:

1 Chapman, D.: ‘The cost of poor power quality’ (European Copper Institute, Copper Development Association, 2001), March

2 Radmehr, M., Farhangi, S., Nasiri, A.: ‘Effects of power quality distortions on electrical drives and transformer life in paper industries’, IEEE Ind. Appl. Mag., 2007, 13, (5), pp. 38–48

3 Lamoree, J., Mueller, D., Vinett, P.: ‘Voltage sag analysis case studies’, IEEE Trans. Ind. Appl., 1994, 30, (4), pp. 1083–1089

4 Bollen, M.H.J.: ‘Understanding power quality problems: voltage sags and interruptions’ (New York, Saranarce University of Technology, 2000)

5 Ghosh, A., Ledwich, G.: ‘Power quality enhancement using custom power devices’ (Berlin, Kluwer Academic Publications, 2002)

Modelling and analysis of modular multilevel converter for solar photovoltaic applications to improve power quality

ABSTRACT:

The design of control circuit for a solar fed cascaded multilevel inverter to reduce the number of semiconductor switches is presented in this study. The design includes ‘binary’, ‘trinary’ and ‘modified multilevel connection’ (MMC)-based topologies suitable for varying input sources from solar photovoltaic’s (PV). In binary mode, 2Ns +1 − 1 output voltage levels are obtained where Ns is the number of individual inverters. This is achieved by digital logic functions which includes counters, flip-flops and logic gates. In trinary mode, 3Ns levels are achieved by corresponding look-up table. MMC intends design in both control and power circuits to provide corresponding output voltage levels by appropriate switching sequences. Hence to obtain a 15-level inverter, the conventional method requires 28 switches and in binary mode 12 switches are needed. In trinary mode with the same 12 switches, 27 levels can be obtained whereas in MMC only 7 switches are employed to achieve 15 levels. The advantage of these three designs is in the reduction of total harmonic distortion by increasing the levels. Simulations are carried out in MATLAB/Simulink and comparisons were made. All the three topologies are experimentally investigated for a 3 kWp solar PV plant and power quality indices were measured.

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

 

 Fig.1 Single stage 15-level inverter power circuit

EXPECTED SIMULATION RESULTS:

 

Fig. 2 Solar PV with partial shaded condition for a 15-level CMLI

a Variation of panel irradiance

b 15-level output voltage waveform

Fig. 3 15-level output voltage waveform achieved from three stage inverter

a 15-level output voltage waveform

b FFT analysis for three stage 15-level CMLI

Fig. 4 Output voltage waveform and its corresponding harmonic spectrum

a 27-level output voltage waveform

b FFT analysis for three stage 27-level CMLI

 

Fig. 5 Output voltage waveform and its corresponding harmonic spectrum

a 15-level output voltage waveform

b FFT analysis for one stage 15-level CMLI

CONCLUSION:

The power quality improvement for a solar fed CMLI with reduced number of semiconductor switches is investigated in this paper. The required 15-level output is achieved with only 12 switches in binary mode and 7 switches in MMC mode. In addition, 27-level output is obtained with 12 switches through trinary mode. The mathematical model for solar PV is carried out which is considered as the input to the inverter stages. A detailed simulation study is carried out for various levels and comparison has been made. A 3 kWp solar PV fed CMLI is implemented for all the three topologies and harmonics analysis was made. Based on the observations, the proposed method provides the multiple advantages which include reduced THD, less cost, simple design, minimum computational complexity and the absence of transformers, boost converters, detailed look-up table and filter circuit. Moreover, these methods are much suitable for standalone/grid interacted PV systems to improve power quality.

REFERENCES:

1 Rahim, N.A., Selvaraj, J.: ‘Multistring five-level inverter with novel PWM control scheme for PV application’, IEEE Trans. Ind. Electron., 2010, 57, (6), pp. 2111–2123

2 Selvaraj, J., Rahim, N.A.: ‘Multilevel inverter for grid-connected PV system employing digital PI controller’, IEEE Trans. Ind. Electron., 2009, 56, (1), pp. 149–158

3 Rahim, N.A., Chaniago, K., Selvaraj, J.: ‘Single-phase seven-level grid-connected inverter for photovoltaic system’, IEEE Trans. Ind. Electron., 2011, 58, (6), pp. 2435–2443

4 Barbosa, P.G., Braga, H.A.C., do Carmo Barbosa Rodrigues, M., Teixeira, E.C.: ‘Boost current multilevel inverter and its application on single-phase grid-connected photovoltaic systems’, IEEE Trans. Power Electron., 2006, 21, (4), pp. 1116–1124

5 Villanueva, E., Correa, P., Rodríguez, J., Pacas, M.: ‘Control of a single-phase cascaded H-bridge multilevel inverter for grid-connected photovoltaic systems’, IEEE Trans. Ind. Electron., 2009, 56, (11), pp. 4399–4406

 

An Envelope Type (E-Type) Module Asymmetric Multilevel Inverters With Reduced Components

ABSTRACT:

This paper presents a new E-Type module for asymmetrical multilevel inverters with reduced components. Each module produces 13 levels with four unequal DC sources and 10 switches. The design of the proposed module makes some preferable features with a better quality than similar modules such as the low number of semiconductors and DC sources and low switching frequency. Also, this module is able to create a negative level without any additional circuit such as an H-bridge which causes reduction of voltage stress on switches. Cascade connection of the proposed structure leads to a modular topology with more levels and higher voltages. Selective harmonics elimination pulse width modulation (SHE-PWM) scheme is used to achieve high quality output voltage with lower harmonics. MATLAB simulations and practical results are presented to validate the proposed module good performance. Module output voltage satisfies harmonics standard (IEEE519) without any filter in output.

KEYWORDS:

  1. Asymmetric
  2. Components
  3. E-Type
  4. Multilevel inverter
  5. Power electronics
  6. Selective harmonics elimination

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

(a)

Fig. 1 Proposed E-Type module of multilevel inverter (a) Circuit topology

EXPECTED SIMULATION RESULTS:

 Fig.2 Output voltage and FFT analysis of proposed multilevel

CONCLUSION:

This paper presented a new multilevel inverter topology named as Envelope Type (E-Type) module which can generate 13 levels with reduced components. It can be used in high voltage high power applications with unequal DC sources. As E-Type module can be easily modularized, it can be used in cascade arrangements to form high voltage outputs with low stress on semiconductors and lowering the number of devices. Modular connection of these modules leads to achieve more voltage levels with different possible paths. It causes an improvement in the reliability of the modular inverter which enables it to use different paths in case of malfunction for a switch or a driver. The main advantage of proposed module is its ability to generate both positive and negative output voltage without any H-bridge circuit at the output of the inverter. THDv% is obtained 3.46% and 4.54% in simulation and experimental results, respectively that satisfy harmonics standard (IEEE519). Also module is tested in three frequency and under different resistive – inductive loads which results shows good performance.

REFERENCES:

[1] R. Feldman, M. Tomasini, E. Amankwah, J.C. Clare, P.W. Wheeler, D.R. Trainer, R.S. Whitehouse, “A Hybrid Modular Multilevel Voltage Source Converter for HVDC Power Transmission,” IEEE Trans. Ind. Appl., vol.49, no.4, pp.1577–1588, July-Aug. 2013.

[2] M. Odavic, V. Biagini, M. Sumner, P. Zanchetta, M. Degano, “Low Carrier–Fundamental Frequency Ratio PWM for Multilevel Active Shunt Power Filters for Aerospace Applications,” IEEE Trans. Ind. Appl., vol.49, no.1, pp.159–167, Jan.-Feb. 2013.

[3] Liming Liu, Hui Li, Seon-Hwan Hwang, Jang-Mok Kim, “An Energy-Efficient Motor Drive With Autonomous Power Regenerative Control System Based on Cascaded Multilevel Inverters and Segmented Energy Storage,” IEEE Trans. Ind. Appl., vol.49, no.1, pp.178–188, Jan.-Feb. 2013.

[4] Yushan Liu, Baoming Ge, H. Abu-Rub, F.Z. Peng, “An Effective Control Method for Quasi-Z-Source Cascade Multilevel Inverter-Based Grid-Tie Single-Phase Photovoltaic Power System,” IEEE Trans. Ind. Inform., vol.10, no.1, pp.399–407, Feb. 2014.

[5] Jun Mei, Bailu Xiao, Ke Shen, L.M. Tolbert, Jian Yong Zheng, “Modular Multilevel Inverter with New Modulation Method and Its Application to Photovoltaic Grid-Connected Generator,” IEEE Trans. on Power Electron., vol.28, no.11, pp.5063–5073, Nov. 2013.

 

Design and Implementation of a Novel Multilevel DC–AC Inverter

ABSTRACT:

In this paper, a novel multilevel dc–ac inverter is proposed. The proposed multilevel inverter generates seven-level ac output voltage with the appropriate gate signals’ design. Also, the low-pass filter is used to reduce the total harmonic distortion of the sinusoidal output voltage. The switching losses and the voltage stress of power devices can be reduced in the proposed multilevel inverter. The operating principles of the proposed inverter and the voltage balancing method of input capacitors are discussed. Finally, a laboratory prototype multilevel inverter with 400-V input voltage and output 220 Vrms/2 kW is implemented. The multilevel inverter is controlled with sinusoidal pulse-width modulation (SPWM) by TMS320LF2407 digital signal processor (DSP). Experimental results show that the maximum efficiency is 96.9% and the full load efficiency is 94.6%.

KEYWORDS:

  1. DC–AC inverter
  2. Digital signal processor (DSP)
  3. Maximum power point tracking (MPPT)
  4. Multilevel

 SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1. Block diagram of renewable system

EXPECTED SIMULATION RESULTS:

 Fig. 2. Waveforms of vgs1, vab, vo, and io at 500 W.

Fig. 3. Output voltage harmonic spectrum of vab calculated by FFT.

Fig. 4. Output voltage harmonic spectrum of vo calculated by FFT

Fig. 5. Waveforms of vC2, vo, and io at 1000 W.

Fig. 6. Waveforms of vC2, vo, and io at 2000 W.

Fig. 7. Waveforms of vo and io at 400 VA.

 CONCLUSION:

A novel seven-level inverter was designed and implemented with DSP in this paper. The main idea of the proposed configuration is to reduce the number of power device. The reduction of power device is proved by comparing with traditional structures. Finally, a laboratory prototype of seven-level inverter with 400-V input voltage and output 220 Vrms/2kW is implemented. Experimental results show that the maximum efficiency is 96.9% and the full load efficiency is 94.6%.

 REFERENCES:

[1] R. Gonzalez, E. Gubia, J. Lopez, and L. Marroyo, “Transformerless single-phase multilevel-based photovoltaic inverter,” IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 2694–2702, Jul. 2008.

[2] S. Daher, J. Schmid, and F. L.M. Antunes, “Multilevel inverter topologies for stand-alone PV systems,” IEEE Trans. Ind. Electron., vol. 55, no. 7, pp. 2703–2712, Jul. 2008.

[3] W. Yu, J. S. Lai, H. Qian, and C. Hutchens, “High-efficiency MOSFET inverter with H6-type configuration for photovoltaic nonisolated, acmodule applications,” IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1253–1260, Apr. 2011.

[4] R. A. Ahmed, S. Mekhilef, and W. P. Hew, “New multilevel inverter topology with minimum number of switches,” in Proc. IEEE Region 10 Conf. (TENCON), 2010, pp. 1862–1867.

[5] M. R. Banaei and E. Salary, “New multilevel inverter with reduction of switches and gate driver,” in Proc. IEEE 18th Iran. Conf. Elect. Eng. (IECC), 2010, pp. 784–789.

Nine-level Asymmetrical Single Phase Multilevel Inverter Topology with Low switching frequency and Reduce device counts

 

ABSTRACT:

This paper presents a new asymmetrical single phase multilevel inverter topology capable of producing nine level output voltage with reduce device counts. In order to obtain the desired output voltage, dc sources are connected in all the combination of addition and subtraction through different switches. Proposed topology results in reduction of dc source, switch counts, losses, cost and size of the inverter. Comparison between the existing topologies shows that the proposed topology yields less component counts. Proposed topology is modeled and simulated using Matlab-Simulink software in order to verify the performance and feasibility of the circuit. A low frequency switching strategy is also proposed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage with less number of component counts and acceptable harmonic distortion content.

KEYWORDS:

  1. Multilevel inverter
  2. Asymmetrical
  3. Total Harmonic Distortion (THD)
  4. Low-frequency switching

 SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Proposed nine level inverter topology.

EXPECTED SIMULATION RESULTS:

 

  • (a) Output voltage waveform
  • (b) Voltage Output Harmonic spectrum
  • (c) Load current waveform
  • (d) Load Current Harmonic spectrum
  • Fig. 2. Simulation Output results at 50Hz fundamental frequency for R =150ohm, L= 240, P.F = 0.9

(a) Output voltage waveform

  • (b) Voltage Output Harmonic spectrum

  • (c) Load current waveform
  • (d) Load Current Harmonic spectrum
  • Fig. 3. Simulation Output results at 50Hz fundamental frequency for R = 150ohm, L= 240, P.F = 0.9

CONCLUSION:

In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be used in medium and high power application with unequal dc sources. Different modes of operation are discussed in detail. On the bases of device counts, the proposed topology is compared with conventional as well as other asymmetrical nine-level inverter topologies presented in literature. Comparative study shows that, for nine level output, the proposed topology requires lesser component counts then the conventional and other topologies. Proposed circuit is modeled in Matlab/Simulink environment. Results obtained shows that topology works properly. Detailed Simulation analysis is carried out. THD obtained in the output voltage is 8.95% whereas the each harmonic order is < 5%, satisfies harmonic Standard (IEEE-519).

 REFERENCES:

[1] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats and M. A. Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications”, IEEE Proceeding, Vol 97, No. 11, pp.1786 – 1817, November 2009.

[2] J. R. Espinoza, “Inverter”, Power Electronics Handbook, M. H. Rashid, Ed. New York, NY, USA: Elsevier, 2001,pp. 225 -269.

[3] L. M. Tolbert and T. G. Habetler, “Novel multilevel inverter carrier based PWM method”, IEEE Transactions on Indsutrial Apllications”, Vol. 35, No. 5, pp. 1098-1107, September 1999.

[4] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard and P. Barbosa, “Operation, Control and Applications of the Modular Multilevel Converter: A Review”, IEEE Transactions on Power Electronics, Vol. 30, No. 1, pp. 37-53, January 2015.

[5] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. C. Portillo and M. A. M. Prats, “The Age of Multilevel Converters Arrives”, IEEE Industrial Electronics magazine, Vol. 2, No. 2 pp. 28-39, June 2008.

An Envelope Type (E-Type) Module Asymmetric Multilevel Inverters With Reduced Components

ABSTRACT:

This paper presents a new E-Type module for asymmetrical multilevel inverters with reduced components. Each module produces 13 levels with four unequal DC sources and 10 switches. The design of the proposed module makes some preferable features with a better quality than similar modules such as the low number of semiconductors and DC sources and low switching frequency. Also, this module is able to create a negative level without any additional circuit such as an H-bridge which causes reduction of voltage stress on switches. Cascade connection of the proposed structure leads to a modular topology with more levels and higher voltages. Selective harmonics elimination pulse width modulation (SHE-PWM) scheme is used to achieve high quality output voltage with lower harmonics. MATLAB simulations and practical results are presented to validate the proposed module good performance. Module output voltage satisfies harmonics standard (IEEE519) without any filter in output.

KEYWORDS:

  1. Asymmetric
  2. Components
  3. E-Type
  4. Multilevel inverter
  5. Power electronics
  6. Selective harmonics elimination

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

 

 

Fig. 1 Proposed E-Type module of multilevel inverter (a) Circuit topology 

EXPECTED SIMULATION RESULTS:

 

 Fig.2 Output voltage and FFT analysis of proposed multilevel

 CONCLUSION:

This paper presented a new multilevel inverter topology named as Envelope Type (E-Type) module which can generate 13 levels with reduced components. It can be used in high voltage high power applications with unequal DC sources. As E-Type module can be easily modularized, it can be used in cascade arrangements to form high voltage outputs with low stress on semiconductors and lowering the number of devices. Modular connection of these modules leads to achieve more voltage levels with different possible paths. It causes an improvement in the reliability of the modular inverter which enables it to use different paths in case of malfunction for a switch or a driver. The main advantage of proposed module is its ability to generate both positive and negative output voltage without any H-bridge circuit at the output of the inverter. THDv% is obtained 3.46% and 4.54% in simulation and experimental results, respectively that satisfy harmonics standard (IEEE519). Also module is tested in three frequency and under different resistive – inductive loads which results shows good performance.

REFERENCES:

[1] R. Feldman, M. Tomasini, E. Amankwah, J.C. Clare, P.W. Wheeler, D.R. Trainer, R.S. Whitehouse, “A Hybrid Modular Multilevel Voltage Source Converter for HVDC Power Transmission,” IEEE Trans. Ind. Appl., vol.49, no.4, pp.1577–1588, July-Aug. 2013.

[2] M. Odavic, V. Biagini, M. Sumner, P. Zanchetta, M. Degano, “Low Carrier–Fundamental Frequency Ratio PWM for Multilevel Active Shunt Power Filters for Aerospace Applications,” IEEE Trans. Ind. Appl., vol.49, no.1, pp.159–167, Jan.-Feb. 2013.

[3] Liming Liu, Hui Li, Seon-Hwan Hwang, Jang-Mok Kim, “An Energy-Efficient Motor Drive With Autonomous Power Regenerative Control System Based on Cascaded Multilevel Inverters and Segmented Energy Storage,” IEEE Trans. Ind. Appl., vol.49, no.1, pp.178–188, Jan.-Feb. 2013.

[4] Yushan Liu, Baoming Ge, H. Abu-Rub, F.Z. Peng, “An Effective Control Method for Quasi-Z-Source Cascade Multilevel Inverter-Based Grid-Tie Single-Phase Photovoltaic Power System,” IEEE Trans. Ind. Inform., vol.10, no.1, pp.399–407, Feb. 2014.

[5] Jun Mei, Bailu Xiao, Ke Shen, L.M. Tolbert, Jian Yong Zheng, “Modular Multilevel Inverter with New Modulation Method and Its Application to Photovoltaic Grid-Connected Generator,” IEEE Trans. on Power Electron., vol.28, no.11, pp.5063–5073, Nov. 2013.

 

High-performance multilevel inverter drive of brushless DC Motor

ABSTRACT:

The brushless DC (BLDC) motor has numerous applications in high-power systems; it is simple in construction, is cheap, requires less maintenance, has higher efficiency, and has high power in the output unit. The BLDC motor is driven by an inverter. This paper presents design and simulation for a three-phase three-level inverter to drive the BLDC motor. The multilevel inverter is driven by discrete three-phase pulse width modulation (DPWM) generator that forced-commuted the IGBT’s three-level converters using three bridges to vectored outputs 12- pulses with three levels. Using DPWM with a three-level inverter solves the problem of harmonic distortions and low electromagnetic interference. This topology can attract attention in high-power and high-performance voltage applications. It provides a three-phase voltage source with amplitude, phase, and frequency that are controllable. The proposed model is used with the PID controller to follow the reference speed signal designed by variable steps. The system design is simulated by using Matlab/Simulink. Satisfactory results and high performance of the control with steady state and transient response are obtained. The results of the proposed model are compared with the variable DC-link control. The results of the proposed model are more stable and reliable.

KEYWORDS:

  1. Brushless DC Motor
  2. Multilevel Inverter
  3. High-Performance Drive
  4. Pulse Width Modulation (PWM)
  5. Maltlab
  6. Simulink

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Figure 1. BLDC motor with MLI driven with PID controller.

EXPECTED SIMULATION RESULTS:

 

 Figure. 2. Output of three-phase three-level inverter with DPWM.

Figure 3. The sample from output of the DPWM

Figure 4. Analysis of response for the proposed MLI with PID controller of BLDC motor.

Fig. 5. Two outputs of controllers with proposed MLI and variable DC-link

CONCLUSION:

The proposed MLI performance analysis was successfully presented by using Matlab/Simulink software. The proposed topology can be easily extended to a higher-level inverter. The simulation results were sine waves and exhibited fewer ripples and low losses. This system would show its feasibility in practice. The vector control was described in adequate detail and was implemented with a three-level MLI. This method enabled the operation of the drive at zero direct axis stator current. Transient results were obtained when a DPWM was started from a standstill to a required speed. The performance of the vector control in achieving a fast reversal of PDPWM even at very high speed ranges is quite satisfactory. The performance of the proposed three-phase MLI was investigated and was found to be quite satisfactory. A comparison was made between the PID controller–based proposed model MLI and the controller with variable DC-link voltage. The results showed that the proposed model responded better in transient and steady states and was more reliability with high performance.

REFERENCES:

[1] P. D. Kiran, M. Ramachandra, “Two-Level and Five-Level Inverter Fed BLDC Motor Drives”, International Journal of Electrical and Electronics Engineering Research, Vol. 3, Issue 3, pp 71-82, Aug 2013

[2] N. Karthika, A. Sangari, R. Umamaheswari , “Performance Analysis of Multi Level Inverter with DC Link Switches for Renewable Energy Resources”, International Journal of Innovative Technology and Exploring Engineering, Volume-2, Issue-6, pp 171-176, May 2013

[3] A. Jalilvand R. Noroozian M. Darabian, “Modeling and Control Of Multi-Level Inverter for Three-Phase Grid-Connected Photovoltaic Sources”, International Journal on Technical and Physical Problems of Engineering, Iss. 15, Vol. 5, No.2, pp 35-43, June 2013

[4] P. Karuppanan, K. Mahapatra, “PI, PID and Fuzzy Logic Controlled Cascaded Voltage Source Inverter Based Active Filter For Power Line Conditioners”, Wseas Transactions On Power Systems, Issue 4, Volume 6, pp 100-109, October 2011

[5] D. Balakrishnan, D. Shanmugam, K.Indiradevi, “Modified Multilevel Inverter Topology for Grid Connected PV Systems”, American Journal of Engineering Research, Vol. 02, Iss.10, pp-378-384, 2013

 

Cascaded Two-Level Inverter-Based Multilevel STATCOM for High-Power Applications

ABSTRACT

In this paper, a simple static var compensating scheme using a cascaded two-level inverter-based multilevel inverter is proposed. The topology consists of two standard two-level inverters connected in cascade through open-end windings of a three-phase transformer. The dc link voltages of the inverters are regulated at different levels to obtain four-level operation. The simulation study is carried out in MATLAB/SIMULINK to predict the performance of the proposed scheme under balanced and unbalanced supply-voltage conditions. A laboratory prototype is developed to validate the simulation results. The control scheme is implemented using the TMS320F28335 digital signal processor. Further, stability behavior of the topology is investigated. The dynamic model is developed and transfer functions are derived. The system behavior is analyzed for various operating conditions.

 KEYWORDS

  1. DC-link voltage balance
  2. Multilevel inverter
  3. Power quality (PQ)
  4. Static compensator (STATCOM)

 SOFTWARE:  MATLAB/SIMULINK

BLOCK DIAGRAM

image002

Fig. 1. Power system and the STATCOM model.

EXPECTED SIMULATION RESULTS

image004

Fig. 2. Frequency response ∆Vdc1(s) /∆δ1(s) at  iq0 =1.02 p.u., δ1=-0.902=178.90,R1=80 p.u., R2=60 p.u.

image006

Fig. 3. Root locus of the transfer function  ∆Vdc1(s) /∆δ1(s) at  iq0 = – 0.75 p.u., δ1=-0.5702=179.60,R1 =80 p.u., R2=60 p.u.

image008

Fig. 4. Reactive power control. (a) Source voltage and inverter current. (b) DC-link voltages of two inverters.

image010

Fig. 5. Operation during fault. (a) Grid voltages on the LV side of the transformer. (b) -axis negative-sequence current component idn. (c) -axis negative- sequence current component iqn.

 

image012

Fig. 6. Experimental result: Capacitive mode of operation. (a) Source voltage (50 V/div) and STATCOM current (5 A/div). (b) DC-link voltages of inverter-1 and inverter-2 (20 V/div). Time scale: 5 ms/div. (c) Harmonic spectrum of current.

image014

Fig. 7. Experimental result: Mode change from capacitive to inductive. (a) DC-link voltages of inverter-1 and inverter-2 (20 V/div). Time scale: 100 ms/div. (b) Source voltage (100 V/div) and STATCOM current (5 A/div) in steady state. Time scale: 100 ms/div.

CONCLUSION

DC-link voltage balance is one of the major issues in cascaded inverter-based STATCOMs. In this paper, a simple var compensating scheme is proposed for a cascaded two-level inverter- based multilevel inverter. The scheme ensures regulation of dc-link voltages of inverters at asymmetrical levels and reactive power compensation. The performance of the scheme is validated by simulation and experimentations under balanced and unbalanced voltage conditions. Further, the cause for instability when there is a change in reference current is investigated. The dynamic model is developed and transfer functions are derived. System behavior is analyzed for various operating conditions. From the analysis, it is inferred that the system is a non minimum phase type, that is, poles of the transfer function always lie on the left half of the -plane. However, zeros shift to the right half of the -plane for certain operating conditions. For such a system, oscillatory instability for high controller gains exists.

REFERENCES

[1] N. G. Hingorani and L. Gyugyi, Understanding FACTS. Delhi, India: IEEE, 2001, Standard publishers distributors.

[2] B. Singh, R. Saha, A. Chandra, and K. Al-Haddad, “Static synchronous compensators (STATCOM): A review,” IET Power Electron., vol. 2, no. 4, pp. 297–324, 2009.

[3] H. Akagi, H. Fujita, S. Yonetani, and Y. Kondo, “A 6.6-kV transformerless STATCOM based on a five-level diode-clamped PWMconverter: System design and experimentation of a 200-V 10-kVA laboratory model,” IEEE Trans. Ind. Appl., vol. 44, no. 2, pp. 672–680, Mar./Apr. 2008.

[4] A. Shukla, A. Ghosh, and A. Joshi, “Hysteresis current control operation of flying capacitor multilevel inverter and its application in shunt compensation of distribution systems,” IEEE Trans. Power Del., vol. 22, no. 1, pp. 396–405, Jan. 2007.

[5] H. Akagi, S. Inoue, and T. Yoshii, “Control and performance of a transformerless cascaded PWM STATCOM with star configuration,” IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. 1041–1049, Jul./Aug. 2007.