Low Switching Frequency Based Asymmetrical Multilevel Inverter Topology With Reduced Switch Count




The inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum efficiency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology.


  1. DC/AC converter
  2. Multilevel inverter
  3. Reduce switch count
  4. Nearest level control (NLC)



The paper presents a novel MLI topology with multiple extension capabilities. The basic unit of the proposed topology produces 13 levels using eight unidirectional switches and three dc voltage sources. Three different extension of the basic unit has been proposed. The performance analysis of the basic unit of the proposed topology has been done and the comparative results with some recently proposed topologies in literature have been presented in the paper. Further, a power loss analysis of the dynamic losses (switching and conduction) in the MLI has also been presented, which gives the maximum efficiency of the basic unit as 98.5%. The power loss distribution in all the switches for different combination of loads have also been demonstrated in the paper. The performance of the proposed topology has been simulated with dynamic modulation indexes and different combination of loads using PLECS software. A prototype of the basic unit has been developed in the laboratory and the simulation results have been validated using the different experimental results considering different modulation indexes.


[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553_2580, Aug. 2010.

[2] H. Aburub, J. Holtz, and J. Rodriguez, “Medium-voltage multilevel converters-state of the art, challenges, and requirements in industrial applications,” IEEE Trans. Ind. Electron, vol. 57, no. 8, pp. 2581_2596, Dec. 2010.

[3] H. Akagi, “Multilevel converters: Fundamental circuits and systems,” Proc. IEEE, vol. 105, no. 11, pp. 2048_2065, Nov. 2017.

[4] J. I. Leon, S. Vazquez, and L. G. Franquelo, “Multilevel converters: Control and modulation techniques for their operation and industrial applications,” Proc. IEEE, vol. 105, no. 11, pp. 2066_2081, Nov. 2017.

[5] J. Venkataramanaiah, Y. Suresh, and A. K. Panda, “A review on symmetric, asymmetric, hybrid and single DC sources based multilevel inverter topologies,” Renew. Sustain. Energy Rev., vol. 76, pp. 788_812, Sep. 2017.

A Novel Seven-Level Active Neutral Point Clamped Converter with Reduced Active Switching Devices and DC-link Voltage


This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying-capacitor units forming a similar structure as in a conventional Active Neutral Point Clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional 7-level inverter topologies such as the Neutral Point Clamped (NPC), Flying Capacitor (FC), Cascaded H-bridge (CHB) and Active NPC (ANPC) topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2 kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range.


  1. Multilevel Inverter
  2. 7-level inverter
  3. Active Neutral Point Clamped (ANPC) inverter
  4. Flying Capacitor
  5. Voltage Source Converter



In this paper, a novel eight-switch seven-level Active Neutral Point Clamped inverter is proposed. Modulation techniques are explored and operation under both active and reactive power factor conditions are systematically analyzed. A comparative analysis and a set of design guidelines are presented and followed by simulation and experimental verification. Compared to conventional seven-level inverter topologies, the ANPC inverter topology requires only eight power devices for a single-phase design and halves the dc-link voltage required to produce a given ac voltage output magnitude when compared to similar circuits. For applications such as for a grid-connected PV system, this may help eliminate additional power conversion stages (boost converters) and therefore increase the efficiency and reliability of the system. Further, this reduces the voltage stress on the dc-link capacitor, which reduces the cost and size of the system design. The inverter can operate at any power factor (leading or lagging) without requiring any changes to the modulation scheme. Compared with other seven-level configurations, the performance demonstrated by the new inverter is highly competitive, potentially making it an appropriate topology choice for a wide-range of power conversion applications, e.g. variable-speed drives, electric vehicles (V2G/G2V technologies), grid-connected renewable energy systems.


[1] M. Schweizer, T. Friedli, and J. W. Kolar, “Comparative Evaluation of Advanced Three-Phase Three-Level Inverter/Converter Topologies Against Two-Level Systems,” IEEE Trans. Ind. Electron., vol. 60, no. 12, pp. 5515-5527, Dec. 2012.

[2] H. Tian, Y. Li, Y. W. Li, “A Novel Seven-Level Hybrid-Clamped (HC) Topology for Medium Voltage Motor Drives,” IEEE Trans. Power Electron., vol. 33, no. 7, pp. 5543-5547, Jul. 2018.

[3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent Advances and Industrial Applications of Multilevel Converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553-2580, Aug. 2010.

[4] J. Rodríguez, J. S. Lai, and F. Z. Peng, “Multilevel Inverters: A Survey of Topologies, Controls, and Applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738, Aug. 2002.

[5] J. I. Leon, S. Vazquez, and L. G. Franquelo, “Multilevel Converters: Control and Modulation Techniques for their Operation and Industrial Applications,” Proc. of the IEEE, vol. 105, no. 11, pp. 2066-2081, Nov. 2017.


Standalone Operation of Modified Seven-Level Packed U-Cell (MPUC) Single-Phase Inverter


In this paper the standalone operation of the modified seven-level Packed U-Cell (MPUC) inverter is given and consider. The MPUC inverter has two DC sources and six switches, which cause seven voltage levels at the output. Compared to cascaded H-bridge and neutral point clamp multilevel inverters, the MPUC inverter produce a higher number of voltage levels using fewer components. The experimental results of the MPUC prototype validate the allocate operation of the multilevel inverter handle with various load types including motor, linear, and nonlinear ones. The design considerations, including output AC voltage RMS value, switching frequency, and switch voltage rating, as well as the harmonic analysis of the output voltage waveform, are taken into account to prove the advantages of the introduced multilevel inverter.


1. Multilevel inverter
2. Packed u-cell
3. Power quality
4. Multicarrier PWM
5. Renewable energy conversion



Figure 1. Single-phase seven-level MPUC inverter in standalone mode of operation


Figure 2. Seven-level MPUC inverter output voltage and current with DC source voltages. Ch1: V1,
Ch2: V2, Ch3: Vab, Ch4: il.

Figure 3. One cycle of output voltage and gate pulses of MPUC inverter switches. Ch1: Vab, Ch2: T1
gate pulses, Ch3: T2 gate pulses, Ch4: T3 gate pulses

Figure 4. MPUC inverter switches’ voltage ratings. Ch1: Vab, Ch2: T1 voltage, Ch3: T2 voltage, Ch4:
T3 voltage. and nonlinear). The step-by-step process for connecting loads is depicted in Figure 7, which show

Fig.5. Test results when a nonlinear load is connected to the MPUC inverter.Ch1 :Vab :Ch4 :il.

Figure 6. Output voltage and current waveform of MPUC inverter when different loads are added
step by step. Ch1: Vab, Ch4: il. (A) Transient state when nonlinear load is added to the RL load (left)
and after a while a motor load is added to the system (right); (B) steady state when a nonlinear load is
added to the RL load (left) and after a while a motor load is added to the system (right).

Figure 7. Voltage and current waveform of MPUC inverter with RMS calculation for 120 V system.


In this paper a redesign PUC inverter topology has been presented and studied experimentally. The proposed MPUC inverter can produce a seven-level voltage waveform at the output with low harmonic contents. The associated switching algorithm has been create and achieve on the introduced MPUC topology with reduced switching frequency aspect. Switches’ frequencies and ratings have been investigated experimentally to validate the good dynamic performance of the proposed topology. Moreover, the comparison of MPUC to the CHB multilevel inverter showed other advantages of the proposed multilevel inverter topology, including fewer components, a lower manufacturing price, and a smaller package due to reduced filter size.
Author improvement: All authors improvement equally to the work presented in this paper.
Funding: This research received no external funding.
competition of Interest: The authors declare no competition of interest.


1. Bose, B.K. Multi-Level Converters; Multidisciplinary Digital Publishing Institute: Basel, Switzerland, 2015.
2. Mobarrez, M.; Bhattacharya, S.; Fregosi, D. Implementation of distributed power balancing strategy with a layer of supervision in a low-voltage DC microgrid. In Proceedings of the 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, USA, 26–30 March 2017; pp. 1248–1254.
3. Franquelo, L.G.; Rodriguez, J.; Leon, J.I.; Kouro, S.; Portillo, R.; Prats, M.A.M. The age of multilevel converters arrives. IEEE Ind. Electron. Mag. 2008, 2, 28–39. [CrossRef]
4. Malinowski, M.; Gopakumar, K.; Rodriguez, J.; Perez, M.A. A survey on cascaded multilevel inverters. IEEE Trans. Ind. Electron. 2010, 57, 2197–2206. [CrossRef]
5. Nabae, A.; Takahashi, I.; Akagi, H. A new neutral-point-clamped PWM inverter. IEEE Trans. Ind. Appl. 1981,5, 518–523. [CrossRef]

New Three-Phase Symmetrical MultilevelVoltage Source Inverter


This paper presents a new design and implementation of a three-phase multilevel inverter (MLI) for distributed power generation system using low frequency modulation and sinusoidal pulse width modulation (SPWM) as well. It is a modular type and it can be extended for extra number of output voltage levels by adding additional modular stages. The impact of the proposed topology is its proficiency to maximize the number of voltage levels using a reduced number of isolated dc voltage sources and electronic switches. Moreover, this paper proposes a significant factor (FC/L), which is developed to define the number of the required components per pole voltage level.

A detailed comparison based on (FC/L) is provided in order to categorize the different topologies of the MLIs addressed in the literature. In addition, a prototype has been developed and tested for various modulation indexes to verify the control technique and performance of the topology. Experimental results show a well-matching and good similarity with the simulation results.

  1. Low frequency modulation
  2. Multi-level inverter
  3. Multi-level inverter comparison factor
  4. Sinusoidal pulse-width modulation (SPWM)
  5. Symmetrical DC power sources
  6. Three-phase



Fig. 1. Proposed three-phase MLI topology.


Fig. 2. Output line-to-line voltages ( VAB,VBC , and VCA ) with low frequency (50 Hz) modulation technique. (a) Simulation.

Fig. 3. Output phase voltages ( VAN,VBN , and VCN ) with low frequency modulation technique. (a) Simulation.

Fig. 4. Inverter outputs with R-L load (VAB ,VAN , and IAN) with low frequency modulation technique. (a) Simulation.

Fig. 5. Pole voltages for scheme I, mi =0.95 and fs=2.5kHz. (a) Simulation.

Fig. 6. Line-to-line voltages for scheme I, mi =0.95 and fs=2.5kHz . (a) Simulation.

Fig. 7. Phase voltages for scheme I, mi =0.95 and fs=2.5kHz . (a) Simulation.

Fig. 8. Pole voltages for scheme II, mi =0.95 and fs=2.5kHz . (a) Simulation.

Fig. 9. Line-to-line voltages for scheme II, mi =0.95 and fs=2.5kHz  . (a) Simulation.

Fig. 10. Phase voltages for scheme II, mi =0.95 and fs=2.5kHz. (a) Simulation.

Fig. 11. Line-to-line voltage and phase voltage at for scheme I, mi =0.95 and fs=2.5kHz . (a) Simulation.

Fig. 12. Line-to-line voltage and phase voltage for scheme II, mi =0.95 and fs=2.5kHz . (a) Simulation.

Fig. 13. Inverter output voltages: (a) three phase line-to-line voltages ( VAB, VBC, and VCA ), (b) line-to-line voltage, phase voltage and the phase current under R-L load.


A new modular multilevel inverter topology using two modulation control techniques is presented. The proposed has several advantages compared with existing topologies. A lower number of components count such as isolated dc-power supplies, switching devices, electrolyte capacitors, and power diodes are required. So it exhibits the merits of high efficiency, lower cost, simplified control algorithm, smaller inverter’s foot print and increased the overall system reliability. Due to the modularity of the presented topology, it can be extended to higher stages number leads to a good performance issues such as low, low, and low and eliminating the output filter will be obtained.

Beside the low frequency modulation, two schemes are successfully applied to control the suggested . This paper also suggests a significant factor, which defines the required components to generate one voltage level across the output pole terminals. The issue related to the cost of each used component is out of scope of this paper. The system simulation model and its control algorithm are developed using PSIM and MATLAB software package tools to validate the proposed topology. A laboratory prototype has been developed and tested for various modulation indexes to verify the control techniques and performance of the topology, the similarity between the simulation and obtained experimental results was confirmed.


[1] S. J. Park, F. S. Kang, M. H. Lee, and C. U. Kim, “A new single-phase five-level PWM inverter employing a deadbeat control scheme,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 831–843, May 2003.

[2] V. G. Agelidis, D. M. Baker, W. B. Lawrance, and C. V. Nayar, “A multilevel PWM inverter topology for photovoltaic applications,” in Proc. Int. Symp. Ind. Electron., Jul. 1997, vol. 2, pp. 589–594.

[3] G. J. Su, “Multilevel DC-link inverter,” IEEE Trans. Ind. Appl., vol. 41, no. 3, pp. 848–854, May–Jun. 2005.

[4] M. Calais, L. J. Borle, and V. G. Agelidis, “Analysis of multicarrier PWM methods for a single-phase five level inverter,” in Proc. Power Electron. Specialists Conf., 2001, vol. 3, pp. 1351–1356.

[5] C. T. Pan, C. M. Lai, and Y. L. Juan, “Output current ripple-free PWM inverters,” IEEE Trans. Circuits Syst. II, Exp. Briefs., vol. 57, no. 10, pp. 823–827, Oct. 2010.

Nine-level Asymmetrical Single Phase Multilevel Inverter Topology with Low switching frequency and Reduce device counts


 This paper presents a new asymmetrical singlephase multilevel inverter topology capable of producing ninelevel output voltage with reduce device counts. In order to obtain the desired output voltage, dc sources are connected in all the combination of addition and subtraction through different switches. Proposed topology results in reduction of dc source, switch counts, losses, cost and size of the inverter. Comparison between the existing topologies shows that the proposed topology yields less component counts. Proposed topology is modeled and simulated using Matlab-Simulink software in order to verify the performance and feasibility of the circuit. A low frequency switching strategy is also proposed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage with less number of component counts and acceptable harmonic distortion content.


  1. Multilevel inverter
  2. Asymmetrical
  3. Total Harmonic Distortion (THD)
  4. Low-frequency switching



Fig. 1. Proposed nine level inverter topology.


Fig. 2. Simulation results for proposed nine level inverter topology; (a)

and (b) are switching pulses, (c) Level generator output voltage.

Fig. 3. Simulation Output results at 50Hz fundamental frequency for R = 150ohm, L= 240, P.F = 0.9

Fig. 4. Simulation Output results at 50Hz fundamental frequency for R =150ohm, L= 240, P.F = 0.9


In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be used in medium and high power application with unequal dc sources. Different modes of operation are discussed in detail. On the bases of device counts, the proposed topology is compared with conventional as well as other asymmetrical nine-level inverter topologies presented in literature. Comparative study shows that, for nine level output, the proposed topology requires lesser component counts then the conventional and other topologies. Proposed circuit is modeled in Matlab/Simulink environment. Results obtained shows that topology works properly. Detailed Simulation analysis is carried out. THD obtained in the output voltage is 8.95% whereas the each harmonic order is < 5%, satisfies harmonic Standard (IEEE-519).


[1] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A.M. Prats and M. A. Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications”, IEEE Proceeding, Vol 97, No. 11, pp.1786 – 1817, November 2009.

[2] J. R. Espinoza, “Inverter”, Power Electronics Handbook, M. H. Rashid, Ed. New York, NY, USA: Elsevier, 2001,pp. 225 -269.

[3] L. M. Tolbert and T. G. Habetler, “Novel multilevel inverter carrierbased PWM method”, IEEE Transactions on Indsutrial Apllications”, Vol. 35, No. 5, pp. 1098-1107, September 1999.

[4] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard and P. Barbosa, “Operation, Control and Applications of the Modular Multilevel Converter: A Review”, IEEE Transactions on Power Electronics, Vol. 30, No. 1, pp. 37-53, January 2015.

[5] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. C. Portillo and M. A. M. Prats, “The Age of Multilevel Converters Arrives”, IEEE Industrial Electronics magazine, Vol. 2, No. 2 pp. 28-39, June 2008.

Investigation on cascade multilevel inverter with symmetric, asymmetric, hybrid and multi-cell configurations


In recent past, numerous multilevel architectures came into existence but in this background, cascaded multilevel invert er (CM LI) is the promising structure. This type of multilevel invert er s synthesizes a medium voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltage and current wave forms, however, when the number of levels increases switching components and the count of dc sources are also increased.

This issue became a key motivation for the present paper which is devoted to investigate different types of CM LI using less number of switching components and dc sources thus finally proposed a new version of Multi-cell based CM LI. In order to verify the proposed topology, MAT LAB – simulations and hardware verification are carried out and results are presented.

  1. Cascade multilevel invert er
  2. Multi-cell
  3. Switching components
  4. High quality output voltages



Figure 1 (a) CH B multilevel invert er, (b) key waveform for seven-level invert er, (c) CH B multilevel invert er by employing single-phase transformers, (d) simulation verification of seven-level CH B multilevel invert er, (e) F  FT spectrum.


Figure 2 (a) Asymmetrical thirteen-level CH B invert er, (b) simulation verification of thirteen-level CH B multilevel invert er, (c) FF T spectrum.


Figure 3 (a) Asymmetrical CH B multilevel invert er, (b) output voltages of each H-bridge module, (c) twenty-seven level output voltage waveform, (d) F FT spectrum.


Figure 4 (a) Asymmetrical CH B multilevel invert er using sub-cells, (b) output voltage of sub-cells, (c) thirty-one level output voltage waveform, (d) FF T spectrum.


Figure 5 (a) Hybrid CH B multilevel invert er, (b) output voltage of each H-bridge and load voltage (nine-level) waveform, (c) FF T spectrum.

Figure 6 (a) Hybrid multilevel invert er using traditional invert er, (b) output voltage waveform, (c) FF T Spectrum.


Figure 7 The proposed multi-cell CM LI.

.Figure 8 (a) The proposed 25-level asymmetric multi-cell CM LI, (b) key wave forms.

Figure 9 (a) Output voltage of first H-bridge, (b) output voltage of second H-bridge, (c) resultant output voltage with 25-levels, (d) FF T spectrum.


 In this paper CM LI with sub-cells is proposed with less number of switches. To highlight the merits of proposed invert er, an in-depth investigation is carried out on symmetric, asymmetric and hybrid multilevel invert er s based on CH B top o log i es. Symmetric configuration has capacity to produce only limited number of levels in output voltage, On the counter side, symmetrical configuration can be operated in asymmetrical mode with different DC sources. However, asymmetrical configurations can produce higher number of output levels and thereby qualitative output wave forms could be generated.


hybrid CH B invert er s are also introduced, which utilizes single DC source for entire structure. Thus complexity and voltage balancing issues can be reduced. Finally proposed invert er is introduced with less number of switching components and able to produce qualitative output wave forms. To verify the proposed invert er adequate simulation is done with help of MAT LAB/sim u link. Later on, hardware variations are carried out in laboratory. Verification are quite impressive with greater number of levels in the output voltage and lower harmonic content in FF T spectrum s. Spectrum s indicate that, low order harmonics are drastically reduced. Thus power quality is significantly enhanced. Thus proposed invert er shows some promising attributes when compared with traditional CH B based architectures.


] B ab a e  E, Ali l u S, La a l i S. A new general topology for cascaded
multilevel invert er s with reduced number of components based on
developed H-bridge. IEEE Trans Ind Electron 2014;61(8):3932–9.
[2] Malinowski Mar i us z, Go p a k u mar K, Rodriguez Jose, P e´re z
Marcelo A. A survey on cascaded multilevel invert er s. IEEE
Trans Ind Electron 2010;57(7):2197–205.
[3] Wu J C, Wu K D, Jo u H L, Xi a o ST. Diode-clamped multi-level
power converter with a zero-sequence current loop for three-phase
three-wire hybrid power filter. Elsevier J Elect r Power S y  s t Res
[4] K ho u c ha Far id, Lag o  n M o u n a So um i a, K he l o i Ab d e l a z i z,
Ben b o u z d Mohamed E l Ha ch e mi. A comparison of symmetrical
and asymmetrical three-phase H-bridge multilevel invert-er for
DTC induction motor drives. IEEE Trans Energy Converse
[5] E bra him i J, Ba b a e i E, G h a r e h p e ti an GB. A new topology of
cascaded multilevel converters with reduced number of components for high-voltage applications. IEEE Trans Power Electron

Transformerless DVR Topology Based on Multilevel Inverter with Reduced Number of Switches


In this paper, a transformerless dynamic voltage restorer (DVR) in light of the staggered inverter is proposed. This staggered inverter utilizes decreased number of switches. Therefore, the proposed DVR has bring down number of switches in correlation with other staggered inverter based DVR topologies. Likewise, it has bring down misfortune and cost because of no requirement for infusion transformers. As reenactment results utilizing Matlab/Simulink programming will appear, the proposed DVR can adjust for voltage lists, swells and glimmers.



Fig. 1. Proposed DVR circuit configuration.



Fig.2 Voltage sag and swell compensation; from top to bottom, source voltage, DVR output voltage before filtering, filtered injection voltage and compensated load voltage.

Fig 3. Voltage flicker compensation; from top to bottom, source voltage, DVR output voltage before filtering, filtered injection voltage and compensated load voltage.



In this paper, a transformerless DVR dependent on the staggered inverter was proposed. Because of utilizing this inverter, the proposed DVR has bring down number of switches in examination with other staggered DVR topologies. Working standards and the power circuit of the proposed DVR was clarified. The DVR was displayed and furthermore control and exchanging system was talked about in subtleties. At last, recreation results demonstrated the DVR capacities in remunerating voltage lists, swells and glimmer.


Thermal Stresses Relief Carrier-Based PWM Strategy for Single Phase Multilevel Inverters


Enhancing power cycling capability of power semiconductor devices is highly demanded in order to increase the long term reliability of multilevel inverters. Ageing of power switches and their cooling systems leads to their accelerated damage due to excess power losses and junction temperatures. Therefore, thermal stresses relief (TSR) is the most effective solution for lifetime extension of power semiconductor devices. This paper presents a new thermal stresses relief carrier-based pulse width modulation (TSRPWM) strategy for extending the lifetime of semiconductor switches in single-phase multilevel inverters. The proposed strategy benefits the inherent redundancy among switching states in multilevel inverters to optimally relieve the thermally stressed device. The proposed algorithm maintains the inverter operation without increased stresses on healthy switches and without reduction of the output power ratings. In addition, the proposed algorithm preserves voltage balance of the DC-link capacitors. The proposed strategy is validated on single phase five level T-type inverter system with considering different locations of thermal stresses detection. Experimental prototype of the selected case study is built to verify the results. Moreover, comparisons with the most featured strategies in literature are given in detail.



 Fig. 1. A schematic diagram of PWM controlled full bridge n-level T-type inverter


 Fig. 2. Simulation results of the proposed strategy at TSD in SA11 at mi=0.85.


 Fig. 3. Simulation results of the proposed strategy at TSD in SA11 at mi=0.45.

Fig. 4. Simulation results of the proposed TSRPWM strategy at TSD in SA12 and mi=0.85.


Single Phase Series Active Power Filter Based on 15-Level Cascaded Inverter Topology


A topology of series active power filter (SAP F) based on a single phase half-bridge cascaded multilevel invert er is proposed in order to compensate voltage harmonics of the load connected to the point of common coupling (P CC). This paper presents the main parts of the invert er and The proposed invert er with the simple control easily obtains any voltage reference. Therefore, the invert er acts as a harmonic source when the reference is a non-sinusoidal signal.


A prototype of 15-level invert er based SAP F is manufactured without using a parallel passive filter (PP F) because it is intended to represent the compensation capability of the SAP F by itself. The load connected to P CC whose voltage is non-sinusoidal is filtered both in simulation and experimental studies. The validity of the proposed invert er based SAP F is verified by simulation as well as experimental study. Both simulation and experimental results show that the proposed multilevel invert er is suitable for SAP F applications.



Figure 1. The basic configuration of the proposed system.


Figure 2. Simulation results – Set I a) V p cc and V h P CC before compensation (50 V I div), b) invert er and load voltage after compensation (50 V I div).

Figure 3. Simulation results – Set 2 a) V p cc and V”p cc before compensation (50 V l div), b) invert er and load voltage after compensation (50 V I div).


This paper proposes a single phase half-bridge cascaded multi level invert er based SAP F. The multi level invert er topology and operation principle is introduced and With the proposed topology, the number of output levels can easily be increased. Switching angles of the semiconductor devices used in the invert er are also obtained by a simple method, moreover A SAP F with the proposed invert er topology is simulated under different harmonic distortion levels of P CC.


The aim of the simulation is to compensate the load voltage harmonics connected to P Cc. In addition to the simulations, the proposed SAP F prototype is designed and Using this prototype, experimental study is also performed. Microchip d s PIC 30 F 6010 is preferred as a controller in this prototype, because it is commercially available and inexpensive micro controller. The presentable results of the proposed system are summarized as follows;


  • The TH D values obtained from simulation study is similar to experimental results and the results of simulation and experimental studies demonstrate the accuracy of the simulation study.
  • The TH D values after compensation is reduced to 2.88% and 3.07% by using the proposed invert er based SAP F and After compensation, the waveform of load voltage is almost sinusoidal.
  • A highly distorted sinusoidal waveform with a TH D value of 24.12% is compensated with the proposed invert er based SAP F and the TH D value is reduced to 3.07%, with This it is shown that the proposed invert er is suitable for SAP F applications.

Both simulation and experimental studies show the validity of the proposed invert er as a SAP F.


[1] M. 1. M. Mon t e r o, E. R. Ca d a val, F. B. Gonzalez, “Comparison of control strategies for shunt active power filters in three-phase four wire systems”, IEEE Trans. Power Electron., , 22, (I), pp. 229- 236, 2007.

[2] F. Z. P e n g, H. A k a g i, and A. Na b a e, ” A new approach to harmonic compensation in power systems-A combined system of shunt passive and series active filters,” IEEE Trans. Ind. A pp l. , Vol. 26, No. 6, pp. 983- 990, N o v.l Dec. 1990.

[3] Z. Wang, Q. Wang, W. Y a o, and 1. Li u, “A series active power filter adopting hybrid control approach,” IEEE Trans. Power Electron. , Vol. 16, No. 3, pp. 301- 310, May 2001.

[4] H. Aka g i, ‘Trends in active power line conditioners,” IEEE Trans. Power Electron. , Vol. 9, No. 3, pp. 263- 268, May 1994.

[5] M. E I-H ab r o u k, M. K. D a r wish, and P. Me h ta, “Active power filters : A review,” l E E Elect r. Power App l., Vol. 147, No. 5, pp. 403-413, Sep.2000.

An Optimized Three Phase Multilevel Inverter Topology with Separate Level and Phase Sequence Generation Part


This manuscript presents an optimized, 3-ϕ, multilevel (MLI) inverter topology.  cascading the level generation part with the phase sequence generation part derives  the proposed system. Further, it can be operated at any required level depending upon the configuration of the level generation part. Thus, for higher level operation extra components are required at the level generation part only. Therefore, number of components required for the proposed MLI is lower than the conventional 3-ϕ MLI topologies for higher level operation. Further, the level generation part is shared in the three phases equally. This eliminates the possibility of phase unbalance. The working principle and the operation of the proposed MLI are supported with the simulation and experimental validations. Further, the proposed optimized MLI is also compared with the conventional 3-ϕ MLIs to prove its advantage.


  1. 3-ϕ
  2. Multilevel inverter
  3. Common mode voltage
  4. New topology



Fig. 1. (a) Circuit schematic for the proposed m-level MLI. (b) Configuration of top/bottom BU.



Fig 2. Simulation results showing the (a) line to line voltages, (b) Output voltage of top BU, (c) output voltage of bottom BU, (d) phase to neutral voltages and (e) load current waveforms of the proposed 3-ϕ MLI in symmetrical operation.


This paper presents an optimized 3-ϕ MLI configuration with reduced number of component. The prominent features of the proposed MLI are as follows.

1) Cascading LGP and PSGP builds the proposed MLI configuration. 

2) For higher level operation only switches required are at the BUs only which resides in the LGP. This reduces the requirement of extra devices compared to conventional topologies.

3) Also, each dc voltage source in the presented MLI topology is equally shared by all the phases. Thus, any chance of inter-phase asymmetry is avoided.

The above mentioned points support that the proposed MLI is an optimized configuration for 3-ϕ operation with reduced number of switches. However, the proposed configuration is operated by using the SVs up-to the red line only. The regular paper presents the further work with an improved PWM strategy which takes all the SVs in account . This will further increase the number of levels at the output and linearity can be maintained in over-modulation region with improved dc-bus utilization.


[1] J. Rodriguez, J. La i and F. Z. Pen g, “Multilevel invert er s: a survey of top o lo  g i es, controls, and applications,” IEEE Trans. Ind. Elect., vol. 49, no. 4, pp. 724-738, Aug. 2002.

[2] K. K. Gupta, A. Ran j an, P. B hat nag a r, L. K. S a h u and S. Jain, “Multilevel Invert er Top o l o g i es With Reduced Device Count: A Review,” IEEE Trans. Power Elect., vol. 31, no. 1, pp. 135-151, Jan. 2016.

[3] Wu, Bin, and Meh d i N a r i man i. High-power converters and AC drives. John Wiley & Sons, 2016.

[4] S. S. Fa z e l, S. Be r net, D. K rug and K. J a l i l i, “Design and Comparison of 4-k V Neutral-Point-Clamped, Flying-Capacitor, and Series-Connected H-Bridge Multilevel Converters,” IEEE Trans. Ind. A p pl., vol. 43, no. 4, pp. 1032-1040, July-a u g. 2007.

[5] L. Wang, D. Zhang, Y. Wang, B. Wu and H. S. At ha b, “Power and Voltage Balance Control of a Novel Three-Phase Solid-State Transformer Using Multilevel Cascaded H-Bridge Invert er s for Micro grid Applications,” in IEEE Trans. Power Elect., vol. 31, no. 4, pp. 3289-3301, April 2016.