An Envelope Type (E-Type) Module Asymmetric Multilevel Inverters With Reduced Components


This paper presents a new E-Type module for asymmetrical multilevel inverters with reduced components. Each module produces 13 levels with four unequal DC sources and 10 switches. The design of the proposed module makes some preferable features with a better quality than similar modules such as the low number of semiconductors and DC sources and low switching frequency. Also, this module is able to create a negative level without any additional circuit such as an H-bridge which causes reduction of voltage stress on switches. Cascade connection of the proposed structure leads to a modular topology with more levels and higher voltages. Selective harmonics elimination pulse width modulation (SHE-PWM) scheme is used to achieve high quality output voltage with lower harmonics. MATLAB simulations and practical results are presented to validate the proposed module good performance. Module output voltage satisfies harmonics standard (IEEE519) without any filter in output.


  1. Asymmetric
  2. Components
  3. E-Type
  4. Multilevel inverter
  5. Power electronics
  6. Selective harmonics elimination





Fig. 1 Proposed E-Type module of multilevel inverter (a) Circuit topology 



 Fig.2 Output voltage and FFT analysis of proposed multilevel


This paper presented a new multilevel inverter topology named as Envelope Type (E-Type) module which can generate 13 levels with reduced components. It can be used in high voltage high power applications with unequal DC sources. As E-Type module can be easily modularized, it can be used in cascade arrangements to form high voltage outputs with low stress on semiconductors and lowering the number of devices. Modular connection of these modules leads to achieve more voltage levels with different possible paths. It causes an improvement in the reliability of the modular inverter which enables it to use different paths in case of malfunction for a switch or a driver. The main advantage of proposed module is its ability to generate both positive and negative output voltage without any H-bridge circuit at the output of the inverter. THDv% is obtained 3.46% and 4.54% in simulation and experimental results, respectively that satisfy harmonics standard (IEEE519). Also module is tested in three frequency and under different resistive – inductive loads which results shows good performance.


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High-performance multilevel inverter drive of brushless DC Motor


The brushless DC (BLDC) motor has numerous applications in high-power systems; it is simple in construction, is cheap, requires less maintenance, has higher efficiency, and has high power in the output unit. The BLDC motor is driven by an inverter. This paper presents design and simulation for a three-phase three-level inverter to drive the BLDC motor. The multilevel inverter is driven by discrete three-phase pulse width modulation (DPWM) generator that forced-commuted the IGBT’s three-level converters using three bridges to vectored outputs 12- pulses with three levels. Using DPWM with a three-level inverter solves the problem of harmonic distortions and low electromagnetic interference. This topology can attract attention in high-power and high-performance voltage applications. It provides a three-phase voltage source with amplitude, phase, and frequency that are controllable. The proposed model is used with the PID controller to follow the reference speed signal designed by variable steps. The system design is simulated by using Matlab/Simulink. Satisfactory results and high performance of the control with steady state and transient response are obtained. The results of the proposed model are compared with the variable DC-link control. The results of the proposed model are more stable and reliable.


  1. Brushless DC Motor
  2. Multilevel Inverter
  3. High-Performance Drive
  4. Pulse Width Modulation (PWM)
  5. Maltlab
  6. Simulink



Figure 1. BLDC motor with MLI driven with PID controller.



 Figure. 2. Output of three-phase three-level inverter with DPWM.

Figure 3. The sample from output of the DPWM

Figure 4. Analysis of response for the proposed MLI with PID controller of BLDC motor.

Fig. 5. Two outputs of controllers with proposed MLI and variable DC-link


The proposed MLI performance analysis was successfully presented by using Matlab/Simulink software. The proposed topology can be easily extended to a higher-level inverter. The simulation results were sine waves and exhibited fewer ripples and low losses. This system would show its feasibility in practice. The vector control was described in adequate detail and was implemented with a three-level MLI. This method enabled the operation of the drive at zero direct axis stator current. Transient results were obtained when a DPWM was started from a standstill to a required speed. The performance of the vector control in achieving a fast reversal of PDPWM even at very high speed ranges is quite satisfactory. The performance of the proposed three-phase MLI was investigated and was found to be quite satisfactory. A comparison was made between the PID controller–based proposed model MLI and the controller with variable DC-link voltage. The results showed that the proposed model responded better in transient and steady states and was more reliability with high performance.


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Cascaded Two-Level Inverter-Based Multilevel STATCOM for High-Power Applications


In this paper, a simple static var compensating scheme using a cascaded two-level inverter-based multilevel inverter is proposed. The topology consists of two standard two-level inverters connected in cascade through open-end windings of a three-phase transformer. The dc link voltages of the inverters are regulated at different levels to obtain four-level operation. The simulation study is carried out in MATLAB/SIMULINK to predict the performance of the proposed scheme under balanced and unbalanced supply-voltage conditions. A laboratory prototype is developed to validate the simulation results. The control scheme is implemented using the TMS320F28335 digital signal processor. Further, stability behavior of the topology is investigated. The dynamic model is developed and transfer functions are derived. The system behavior is analyzed for various operating conditions.


  1. DC-link voltage balance
  2. Multilevel inverter
  3. Power quality (PQ)
  4. Static compensator (STATCOM)




Fig. 1. Power system and the STATCOM model.



Fig. 2. Frequency response ∆Vdc1(s) /∆δ1(s) at  iq0 =1.02 p.u., δ1=-0.902=178.90,R1=80 p.u., R2=60 p.u.


Fig. 3. Root locus of the transfer function  ∆Vdc1(s) /∆δ1(s) at  iq0 = – 0.75 p.u., δ1=-0.5702=179.60,R1 =80 p.u., R2=60 p.u.


Fig. 4. Reactive power control. (a) Source voltage and inverter current. (b) DC-link voltages of two inverters.


Fig. 5. Operation during fault. (a) Grid voltages on the LV side of the transformer. (b) -axis negative-sequence current component idn. (c) -axis negative- sequence current component iqn.



Fig. 6. Experimental result: Capacitive mode of operation. (a) Source voltage (50 V/div) and STATCOM current (5 A/div). (b) DC-link voltages of inverter-1 and inverter-2 (20 V/div). Time scale: 5 ms/div. (c) Harmonic spectrum of current.


Fig. 7. Experimental result: Mode change from capacitive to inductive. (a) DC-link voltages of inverter-1 and inverter-2 (20 V/div). Time scale: 100 ms/div. (b) Source voltage (100 V/div) and STATCOM current (5 A/div) in steady state. Time scale: 100 ms/div.


DC-link voltage balance is one of the major issues in cascaded inverter-based STATCOMs. In this paper, a simple var compensating scheme is proposed for a cascaded two-level inverter- based multilevel inverter. The scheme ensures regulation of dc-link voltages of inverters at asymmetrical levels and reactive power compensation. The performance of the scheme is validated by simulation and experimentations under balanced and unbalanced voltage conditions. Further, the cause for instability when there is a change in reference current is investigated. The dynamic model is developed and transfer functions are derived. System behavior is analyzed for various operating conditions. From the analysis, it is inferred that the system is a non minimum phase type, that is, poles of the transfer function always lie on the left half of the -plane. However, zeros shift to the right half of the -plane for certain operating conditions. For such a system, oscillatory instability for high controller gains exists.


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