A Novel Multilevel Inverter Based on Switched DC Sources

ABSTRACT:  

This paper presents a multilevel invert er that has been conceptualized to reduce component count, particularly for a large number of output levels. It comprises floating input dc sources alternately connected in opposite polarities with one another through power switches whereas each input dc level appears in the stepped load voltage either individually or in additive combinations with other input levels. This approach results in reduced number of power switches as compared to classical to p o log i e s. A single-phase five-level invert er demonstrates the working principle of the proposed topology. The simulation investigates the topology and an exhaustive comparison of the proposed topology is made against the classical cascaded H-bridge topology.

 SOFTWARE: MAT LAB/SIM U LINK

 CIRCUIT DIAGRAM:

 

Fig. 1. Single-phase invert er based on the proposed topology with two input sources.

 EXPECTED SIMULATION RESULTS:

 

 Fig. 2. (a) Reference and carrier wave forms for the proposed scheme for a five-level output. (b) Aggregated signal “a(t).”

Fig. 3. Switching pulse pattern for the five-level invert er.

Fig. 4. Simulation results. (a) Five-level voltage output. (b) Harmonic spectrum of the load voltage.

Fig. 5. Simulation results. (a) Load current waveform with an R L load (R =

2 Ω and L = 2 m H). (b) Harmonic spectrum of the load current.

 

CONCLUSION:

As M LI s are gaining interest, efforts are being directed toward reducing the device count for increased number of output levels, therefore A novel topology for M LI s has been proposed in this paper to reduce the device count. The working principle of the proposed topology has been explained, and mathematical formulations corresponding to output voltage, source currents, voltage stresses on switches, and power losses have been developed. Simulation studies performed on a five-level invert er based on the proposed structure have been validated experimentally.

Comparison

Comparison of the proposed topology with conventional top o l o g i es reveals that the proposed topology significantly reduces the number of power switches and associated gate driver circuits. Analytical comparisons on the basis of losses and switch cost indicate that the proposed topology is highly competitive. The proposed topology can be effectively employed for applications where isolated dc sources are available. The advantage of the reduction in the device count, however, imposes two limitations: 1) requirement of isolated dc sources as is the case with the C H B topology and 2) curtailed modular it y  and fault-tolerant capabilities as compared to the C H B topology.

REFERENCES

[1]S. K o u r o, M. Malinowski, K. Go pa k u m a r, J. P o u, L. Fran q u e lo, B. Wu, J. Rodriguez, M. Perez, and J. Leon, “Recent advances and industrial
applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57,
no. 8, pp. 2553–2580, Aug. 2010.
[2] G. But i c chi, E. Loren z an i, and G. France s chin i, “A five-level single-phase
grid-connected converter for renewable distributed systems,” IEEE Trans.
Ind. Electron., vol. 60, no. 3, pp. 906–918, Mar. 2013.

[3] J. Rodriguez, J.-S. La i, and F. Z h en g Peng, “Multilevel invert er s: A survey
of top o log i es, controls, applications,” IEEE Trans. Ind. Electron., vol. 49,
no. 4, pp. 724–738, Aug. 2002.
[4] S. De, D. Banerjee, K. Siva Kumar, K. Gopakumar, R. Ramchand, and
C. Patel, “Multilevel inverters for low-power application,” IET Power
Electronics, vol. 4, no. 4, pp. 384–392, Apr. 2011.
[5] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Pérez, “A survey
on cascaded multilevel inverters,” IEEE Trans. Ind. Electron., vol. 57,
no. 7, pp. 2197–2206, Jul. 2010

A Quasi-Resonant Switched-Capacitor Multilevel Inverter With Self-Voltage Balancing for Single-Phase High-Frequency AC Microgrids

ABSTRACT:

In this paper, a quasi-resonant switched-capacitor (QRSC) multilevel inverter (MLI) is proposed with self-voltage balancing for single-phase high-frequency ac (HFAC) microgrids. It is composed of a QRSC circuit (QRSCC) in the frontend and an H-bridge circuit in the backend. The input voltage is divided averagely by the series-connected capacitors in QRSCC, and any voltage level can be obtained by increasing the capacitor number. The different operational mechanism and the resulting different application make up for the deficiency of the existing switched-capacitor topologies. The capacitors are connected in parallel partially or wholly when discharging to the load, thus the self-voltage balancing is realized without any high-frequency balancing algorithm. In other words, the proposed QRSC MLI is especially adapted for HFAC fields, where fundamental frequency modulation is preferred when considering the switching frequency and the resulting loss. The quasi-resonance technique is utilized to suppress the current spikes that emerge from the instantaneous parallel connection of the series-connected capacitors and the input source, decreasing the capacitance, increasing their lifetimes, and reducing the electromagnetic interference, simultaneously. The circuit analysis, power loss analysis, and comparisons with typical switched-capacitor topologies are presented. To evaluate the superior performances, a nine-level prototype is designed and implemented in both simulation and experiment, whose results confirm the feasibility of the proposed QRSC MLI.

KEYWORDS:

  1. High-frequency ac (HFAC) microgrids
  2. Quasi-resonant switched-capacitor (QRSC)
  3. Multilevel inverter (MLI)
  4. Self-voltage balancing

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

 Fig. 1. Power sources for a single-phase 500-Hz microgrid.

CIRCUIT DIAGRAM:

Fig. 2. Circuit of the proposed QRSC MLI when outputting 2n+1 levels.

 EXPECTED SIMULATION RESULTS

 

 Fig. 3. Simulation waveforms of the output voltages and currents under different load-types. (a) Vin = 100 V, fo = 500 Hz, ZL = 24 . (b) Vin = 100 V, fo = 500 Hz, ZL = 7.4+j11.3  (|ZL| = 13.5

Fig. 4. (a) Simulation waveforms of the voltages on capacitors C1~C4. (b) Simulation frequency spectrum of the staircase output.

Fig. 5. Simulation waveforms of the capacitors’ charging currents. (a) With quasi-resonant inductor. (b) Without quasi-resonant inductor.

 CONCLUSION:

To make up for the deficiency that existing SC MLIs are inappropriate for the preferred series-connected input occasions like mode 2 in Fig. 1, a novel SC MLI is proposed in this paper with different structure and operational mechanism from the traditional ones, and to suppress the current spikes caused by the capacitors’ instant charging from the input source, a quasi-resonant inductor is embedded into the capacitors’ charging loop, reducing the EMI and longing the capacitors’ lifetimes. Meanwhile, the proposed QRSC MLI combines the advantages of the traditional SC MLI, such as self-voltage balancing under FFM and smaller voltage ripples for capacitors when used as HF power conversion, thus, especially adapted for HFAC microgrids.  The circuit configuration and the power loss analysis of the proposed QRSC MLI have been presented in this paper, as well as the comparisons with typical SC topologies. Lastly, a nine-level prototype is designed and implemented in both simulation and experiment. The results have validated the superior performances of the proposed topology.

REFERENCES:

[1] J. Drobnik, “High frequency alternating current power distribution,” Proceedings of IEEE INTELEC, pp. 292-296, 1994.

[2] S. Chakraborty, M. D. Weiss, and M. G. Simões, “Distributed intelligent energy management system for a single-phase high-frequency AC microgrid,” IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 97-109, Feb. 2007.

[3] S. Chakraborty and M. G. Simões, “Experimental evaluation of active filtering in a single-phase high-frequency AC microgrid,” IEEE Trans. Energy Convers., vol. 24, no. 3, pp. 673-682, Sept. 2009.

[4] S. B. Kjaer, J. K. Pedersen, and Frede Blaabjerg, “A review of single-phase grid-connected inverters for photovoltaic modules,” IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1292–1306, Sep./Oct. 2005.

[5] J. Liu, K. W. E. Cheng, and J. Zeng, “A unified phase-shift modulation for optimized synchronization of parallel resonant inverters in high frequency power distribution system.” IEEE Trans. Ind. Electron., vol. 61, no. 7, pp. 3232,3247, Jul. 2014.

 

Implementation and Comparison of Symmetric and Asymmetric Multilevel Inverters for Dynamic Loads

ABSTRACT:

This paper implements and compares a symmetric hybridized cascaded multilevel inverter and an asymmetric multilevel inverter utilizing a switched capacitor unit for 17 level inverters. The symmetric hybridized multilevel inverter topology consists of a modified H-bridge inverter, which results in an increase in the output voltage to five level from the three level by using a bi-directional switch at the midpoint of a dual-input dc source. In the proposed asymmetric multilevel inverter, dc sources are replaced with the switched capacitor unit, which in turn boosts the output voltage and produces twice the voltage levels at the loads. The proposed topology with the staircase modulation technique has been verified using MATLAB_SIMULINK, and the results are experimentally executed with prototype models, which are interfaced with dSPACE RTI 1104. The results of the proposed topologies are experimentally obtained for steady state, and the performance of the same is tested under different resistive and inductive load disturbance conditions. The results substantiate that these multilevel inverter topologies are better stabilized during load disturbance conditions with low total harmonic distortion, a lesser number of switches, and increased output voltage levels, and these topologies well suit for renewable energy applications.

 

KEYWORDS:

  1. Multilevel inverter (MLI)
  2. Staircase pulse width modulation technique (SPWM)
  3. Switched capacitor unit (SCU)

SOFTWARE: MATLAB/SIMULINK

 

BLOCK DIAGRAM:

Fig. 1. Proposed 17-level symmetric MLI.

asymmetric Switched Capacitor MLI.

Fig. 2. Proposed 17-level asymmetric Switched Capacitor MLI.

 

EXPECTED SIMULATION RESULTS:

 17-level symmetric MLI.

Fig. 3. Individual stage output voltages, output voltage and current of 17-level symmetric MLI.

 

Fig. 4. Waveforms of proposed switched capacitor unit topology.

 

Fig. 5. (a). Waveforms of proposed switched capacitor unit 1 for 17 level MLI. (b). Waveforms of proposed switched capacitor unit 2 for 17 level MLI. (c). Output voltage and current waveforms of 17-level asymmetric Switched Capacitor MLI.

Fig. 6. Steady-state voltage and current response of 17 level symmetric inverter with a resistive load.

Fig. 7. Steady-state voltage and current response of 17 level Symmetric inverter with inductive load.

Fig. 8 Unity power factor to lagging power factor load disturbance response of 17 level symmetric inverter.

Fig. 9. Lagging power factor to unity power factor load disturbance response of 17 level symmetric inverter.

Fig. 10. Steady state voltage and current response of 17 level asymmetric inverter with resistive load.

 

Fig. 11. Steady-state voltage and current response of 17 level asymmetric inverter with inductive load.

Fig. 12. Unity power factor to lagging power factor load disturbance response of 17 level asymmetric inverter.

Fig. 13. Lagging power factor to unity power factor load disturbance response of 17 level asymmetric inverter.

 

CONCLUSION:

This research presents the implementation and analysis of a 17 level symmetric and asymmetric multilevel inverters. The proposed 17 level inverter systems have been effectively tested with unity and lagging power factor loads. In case A, testing has been carried out under steady-state condition, load disturbance conditions and analysis of THD with 17 level symmetric inverter output were presented. It is inferred from case A results that the system is readily adaptive and maintains a stable output voltage with 5.41 % THD for the aforesaid conditions while in case B, a THD with 4.54 % has been achieved, which is on par with IEEE standards. During load disturbances, the proposed topology is suitable for sudden load variant applications also. Due to low THD, these topologies inherently utilize a lesser number of switches and a minimum number of dc input voltage sources; hence, the volume density of the proposed inverter is observed to have improved. From case A and B results it can be inferred that the proposed topology multilevel inverters are suitable for renewable energy-fed applications.

 

REFERENCES:

  • Rodríguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724_738, Aug. 2002.
  • Babaei, S. Laali, and S. Alilu, “Cascaded multilevel inverter with series connection of novel H-bridge basic units,” IEEE Trans. Ind. Electron., vol. 61, no. 12, pp. 6664_6671, Dec. 2014.
  • Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications,” IEEE Trans. Power Electron., vol. 26, no. 11, pp. 3109_3118, Nov. 2011.
  • P. Reddy, M. R. A, M. Sahoo, and S. Keerthipat, “A fault tolerant multilevel inverter for improving the performance of pole-phase modulated nine-phase induction motor drive,” IEEE Trans. Ind. Electron., to be published, doi: 10.1109/TIE.2017.2733474.
  • M. Basri1 and S. Mekhile, “Digital predictive current control of multilevel four-leg voltage-source inverter under balanced and unbalanced load conditions,” IET Electr. Power Appl., vol. 11, no. 8, pp. 1499_1508, 2017.