Compensation Of Voltage Sag And Harmonics By Dynamic Voltage Restorer Without Zero Sequence Blocking

ABSTRACT:

Dynamic Voltage Restorer (DVR) is a power electronic gadget to protection delicate stress from voltage hang. Regularly, delicate burdens are electronic-based gadgets which create music. This paper presents soft polar based DVR as voltage hang restorer and sounds compensator without zero succession blocking. Research exhibited in this paper utilizes d-q-0 pivot technique considering of the estimation of unbiased hub, in light of the fact that the strategy works great if the impartial hub esteem is zero. Result demonstrates that this strategy can repay voltage sag and harmonics with a pay blunder of 0.99%. Utilizing this technique, DVR may lessen voltage THD from 10.22% to 0.66%.

 BLOCK DIAGRAM:

 

 Fig.1 Dynamic voltage restorer

EXPECTED SIMULATION RESULTS:

 

 Fig. 2 Distorted voltages at bus C

Fig. 3 Voltage at bus C after DVR

Fig.4 70% sag at bus C caused by phase-phase-ground fault

Fig.5 70% sag at bus C (caused by phase-phase- ground fault) restored by DVR

CONCLUSION:

The reproduction of a DVR utilizing MATLAB has been introduced. Recreation results demonstrate that DVR can reestablish both the voltage droop and voltage sounds. The proficiency and viability in voltage hang rebuilding and voltage sounds remuneration appeared by the DVR makes it an intriguing force quality gadget contrasted with other custom power gadgets. Under typical condition, DVR can diminish voltage THD from 10.22 % to 0.66%. What’s more, utilizing the proposed strategy, DVR can reestablish hilter kilter voltage droop without zero blocking transformer. The normal mistake of DVR voltage list remuneration is 0.99. voltage sag and harmonics.

Operation and Control of a Dynamic Voltage Restorer Using Transformer Coupled H-Bridge Converters

ABSTRACT:

The dynamic voltage restorer (DVR) as a methods for arrangement remuneration for relieving the impact of voltage lists has turned out to be built up as a favored methodology for enhancing power quality at delicate load areas. In the mean time, the fell staggered kind of intensity converter topology has additionally turned into a workhorse topology in high power applications. This paper exhibits the nitty gritty structure of a shut circle controller to keep up the heap voltage inside adequate dimensions in a DVR utilizing transformer coupled H bridge converters. The paper presents framework task and controller configuration approaches, checked utilizing PC reproductions, and a research center scale exploratory model.

  

BLOCK DIAGRAM:

(b)

Fig. 1 Interconnection schematic of (a) series and (b) shunt compensation configurations

for power quality improvement.

EXPECTED SIMULATION RESULTS:

Fig.2 Simulation results for balanced sag. From top to bottom traces are grid voltage, positive sequence of grid voltage, negative sequence of grid voltage, injected voltage, and load voltage.

Fig 3. Simulation results for unbalanced sag. From top to bottom traces are grid voltage, positive sequence of grid voltage, negative sequence of grid voltage, injected voltage, and load voltage.

 

CONCLUSION:

This paper has exhibited the acknowledgment and control highlights of a DVR utilizing an air conditioner stacked staggered converter with fell H bridge converters. The power circuit engineering has been talked about pursued by a model advancement prompting the controller plan. The framework is displayed in the synchronous reference outline representing positive and negative succession voltage hangs to be alleviated. The multi-circle controller with complex state criticism decoupling is structured with an inward current circle and external voltage circle. The controller highlights strong structure edges, incredible yield impedance, and line direction as outlined utilizing recurrence reaction predications. Point by point numerical reproduction has been completed to check the power circuit activity and control plot. A research facility scale test model was produced that checks the power circuit task and controller execution. Test results demonstrate superb concurrence with advanced reenactments.

Single Phase Dynamic Voltage Restorer Topology Based on Five-level Ground point Shifting Inverter

ABSTRACT

A Single Phase Dynamic Voltage Restorer (DVR) based on five-level ground point shifting multilevel inverter topology has been proposed in this paper. The proposed inverter has a floating ground point. Therefore, by shifting the ground point, it is observed that the inverter circuit gives five output voltage levels from single DC voltage source. This configuration uses less number of switches compared to the existing multilevel inverter topologies. A fast sag swell identification technique using d-q reference frame is also discussed in this paper. This proposed topology of the DVR can compensate voltage sag, swell, flicker and maintain the required voltage at the load bus. The detailed simulation study is carried out using MATLAB/Simulink to validate the result.

 KEYWORDS

  1. Voltage sag
  2. Swell
  3. Ground Point Shifting Multilevel Inverter (GPSMI)
  4. Topology
  5. DVR

 SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM


Fig. 1. General structure of the proposed DVR.

EXPECTED SIMULATION RESULTS

Fig. 2. (a) Grid terminal voltage (vt) and (b) load voltage (vl) during sag

mitigation.

Fig. 3. direct axis value of the d-q reference frame which is used to detect

sag in the system.

Fig. 4. During voltage sag (a) grid terminal voltage (vt), (b) series injected

voltage (vinj) and (c) inverter terminal voltage (vinv).

Fig. 5. FFT analysis of the series injected voltage (vinj).

Fig. 6. (a) Grid terminal voltage and (b) load voltage during Voltage flicker

 CONCLUSION

This paper proposes dynamic voltage restorer based on the ground point shifting multilevel Inverter topology (GPSMI). And explained  the operation of the multilevel inverter and the power circuit diagram. The inverter topology requires less number of switches than conventional multi-level inverter. In this inverter topology, only two switches are active at any instant of time that reduce switch conduction loss. Using this multi-level inverter, reduced the passive filter requirement in the DVR topology. Proper PWM for this proposed inverter has been explained. Instantaneous sag identification technique using d-q reference frame has also been explained. This proposed DVR can mitigate the power quality problem like sag/swell and voltage flicker.

REFERENCES

 [1] IEEE Guide for Voltage Sag Indices,” in IEEE Std 1564-2014 , vol., no., pp.1-59, June 20 2014

[2] IEEE Guide for Identifying and Improving Voltage Quality in Power Systems,” in IEEE Std 1250-2011 (Revision of IEEE Std 1250-1995) , vol., no., pp.1-70, March 31 2011

[3] A. G ho sh and G. Led w i ch, ”Structures and control of a dynamic voltage regulator (DVR),” Power Engineering Society Winter Meeting, 2001. IEEE, Columbus, OH, 2001, pp. 1027-1032 vol.3. do i: 10.1109/PE  S W.2001.917209

[4] Hui wen Li u, Bowen Z hen g and X  ion  g Z h an, ”A comparison of two types of storage less DVR with a passive shunt converter,” 2016 IEEE 8th International Power Electronics and Motion Control Conference (I P EM C-EC CE Asia), He f e i, 2016, pp. 1280-1284.

[5] P. C. Lo h, D. M. Vi lath g  a m  u  w  a , S. K. tang, H. L. Long, ”Multilevel dynamic voltage restorer”, IEEE Power Electronic Letters, vol. 2, no. 4, pp. 125-130, Dec. 2004.

Modeling And Simulation For Voltage Sags/Swells Mitigation Using Dynamic Voltage Restorer (Dvr)

ABSTRACT

 This project describes the problem of voltage sags and swells and its severe impact on non linear loads or sensitive loads. The dynamic voltage restorer (DVR) has become popular as a cost effective solution for the protection of sensitive loads from voltage sags and swells. The control of the compensation voltages in DVR based on dqo algorithm is discussed. It first analyzes the power circuit of a DVR system in order to come up with appropriate control limitations and control targets for the compensation voltage control. The proposed control scheme is simple to design. Simulation results carried out by Matlab/Simulink verify the performance of the proposed method .

KEYWORDS

  1. DVR
  2. Voltage sags
  3. Voltage swells
  4. Sensitive load

 

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM

 DVR

Figure 1: Schematic diagram of DVR

 

FLOWCHART:

  

Fig.2 Flow Chart Of Feed forward Control Technique For DVR Based Ob DQO Transformation

Three-phase voltages sag:

Figure 3. Three-phase voltages sag: (a)-Source voltage,(b)-Injected voltage, (c)-Load voltage

Single-phase voltage sag

Figure.4. Single-phase voltage sag: (a)-Source voltage, (b)-Injected voltage, (c)-Load voltage

Three-phase voltages swell

Figure.5.Three-phase voltages swell: (a)-Source voltage, (b)-Injected voltage, (c)-Load voltage

Two-phase voltages swell

Figure. 6. Two-phase voltages swell: (a)-Source voltage, (b)-Injected voltage, (c)-Load voltage

 

CONCLUSION:

 The modeling and simulation of a DVR using MATLAB/SIMULINK has been presented. A control system based on dqo technique which is a scaled error of the between source side of the DVR and its reference for sags/swell correction has been presented. The simulation shows that the DVR performance is satisfactory in mitigating voltage sags/swells.

 

REFERENCES:

  • G. Hingorani, “Introducing Custom Power in IEEE Spectrum,” 32p, pp. 4l-48, 1995.
  • IEEE Std. 1159 – 1995, “Recommended Practice for Monitoring Electric Power Quality”.
  • Boonchiam and N. Mithulananthan, “Understanding of Dynamic Voltage Restorers through MATLAB Simulation,” Thammasat Int. J. Sc. Tech., Vol. 11, No. 3, July-Sept 2006.
  • G. Nielsen, M. Newman, H. Nielsen,and F. Blaabjerg, “Control and testing of a dynamic voltage restorer (DVR) at medium voltage level,” IEEE Trans. Power Electron., vol. 19, no. 3,p.806, May 2004.
  • Ghosh and G. Ledwich, “Power Quality Enhancement Using Custom Power Devices,” Kluwer Academic Publishers, 2002.
  • Modeling And Simulation For Voltage Sags/Swells Mitigation Using Dynamic Voltage Restorer (Dvr)

Evaluation of DVR Capability Enhancement -Zero Active Power Tracking Technique

IEEE, 2016

ABSTRACT:

This paper presents a utilization technique for enhancing the capabilities of dynamic voltage restorers (DVRs). This study aims to enhance the abilities of DVRs to maintain acceptable voltages and last longer during compensation. Both the magnitude and phase displacement angle of the synthesized DVR voltage are precisely adjusted to achieve lower power utilization. The real and reactive powers are calculated in real time in the tracking loop to achieve better conditions. This technique results in less energy being taken out of the DC-link capacitor, resulting in smaller size requirements. The results from both the simulation and experimental tests illustrate that the proposed technique clearly achieved superior performance. The DVR’s active action period was considerably longer, with nearly 5 times the energy left in the DC-link capacitor for further compensation compared to the traditional technique. This technical merit demonstrates that DVRs could cover a wider range of voltage sags; the practicality of this idea for better utilization is better than that of existing installed DVRs.

 

KEYWORDS:

  1. DVR capability
  2. Energy optimized
  3. Energy source
  4. Series compensator
  5. Voltage stability

 

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

 

Fig 1: Single-line diagram of a power system with the DVR connected at PCC.

 

EXPECTED SIMULATION RESULTS:

Fig.2. D-axis voltages at the system (VSd), DVR (VDVRd), and load (VLd). during in-phase compensation (simulation).

Fig. 3. Q-axis voltages at the system (VSq), DVR (VDVRq), and load (VLq) during in-phase compensation (simulation).

Fig. 4. The overall three-phase voltage signals during in-phase compensation (simulation).

Fig.5 Real power at source (PS), the DVR (PDVR) and load (PL) during in- phase compensation (simulation).

Fig. 6 The DVR DC-side voltage (VDC) during in-phase compensation (simulation).

.

Fig. 7. D-axis voltages at the system(VSd), DVR (VDVRd), and load (VLd) during zero-real power tracking compensation (simulation).

Fig. 8.. Q-axis voltages at the system (VSq), DVR (VDVRq), and load (VLq) during zero-real power tracking compensation (simulation).

Fig. 9. The overall three-phase voltage signals during zero-real power tracking compensation (simulation).

Fig. 10. Real power at source (PS), the DVR (PDVR) and load (PL) zero-real power tracking compensation (simulation).

 

CONCLUSION:

It is clear from both the simulation and experimental results illustrated in this paper that the proposed zero-real power tracking technique applied to DVR-based compensation can result in superior performance compared to the traditional in-phase technique. The experimental test results match those proposed using simulation, although some discrepancies due to the imperfect nature of the test circuit components were seen.

With the traditional in-phase technique, the compensation was performed and depended on the real power injected to the system. Then, more of the energy stored in the DC-link capacitor was utilized quickly, reaching its limitation within a shorter period. The compensation was eventually forced to stop before the entire voltage sag period was finished. When the compensation was conducted using the proposed technique, less energy was used for the converter basic switching process.

The clear advantage in terms of the voltage level at the DC-link capacitor indicates that with the proposed technique, more energy remains in the DVR (67% to 14% in the traditional in-phase technique), which guarantees the correct compensating voltage will be provided for longer periods of compensation. With this technique, none (or less) of the real power will be transferred to the system, which provides more for the DVR to cover a wider range of voltage sags, adding more flexible adaptive control to the solution of sag voltage disturbances.

 

REFERENCES:

  • Bollen, Understanding Power Quality Problems, Voltage Sags and Interruptions. New York: IEEE Press, 1999.
  • Roldán-Pérez, A. García-Cerrada, J. L. Zamora-Macho, P. Roncero-Sánchez, and E. Acha, “Troubleshooting a digital repetitive controller for a versatile dynamic voltage restorer,” Int. J. Elect. Power Energy Syst., vol. 57, pp. 105–115, May 2014.
  • Kanjiya, B. Singh, A. Chandra, and K. Al-Haddad, “SRF theory revisited to control self-supported dynamic voltage restorer (DVR) for unbalanced and nonlinear loads,” IEEE Trans. Ind. Appl., vol. 49, no. 5, pp. 2330–2340, Sep. 2013.
  • Naidu, and D. Fernandes, “Dynamic voltage restorer based on a four-leg voltage source converter,” IET Generation, Transmission & Distribution, vol. 3, no. 5, pp. 437–447, May 2009.
  • Jimichi, H. Fujita, and H. Akagi, “A dynamic voltage restorer equipped with a high-frequency isolated dc-dc converter,” IEEE Trans. Ind. Appl., vol. 47, no. 1, pp. 169–175, Jan. 2011.

 

An Enhanced Voltage Sag Compensation Scheme for Dynamic Voltage Restorer

IEEE Transactions on Industrial Electronics, 2013

ABSTRACT

This paper deals with improving the voltage quality of sensitive loads from voltage sags using dynamic voltage restorer (DVR). The higher active power requirement associated with voltage phase jump compensation has caused a substantial rise in size and cost of dc link energy storage system of DVR. The existing control strategies either mitigate the phase jump or improve the utilization of dc link energy by (i) reducing the amplitude of injected voltage, or (ii) optimizing the dc bus energy support. In this paper, an enhanced sag compensation strategy is proposed that mitigates the phase jump in the load voltage while improving the overall sag compensation time. An analytical study shows that the proposed method significantly increases the DVR sag support time (more than 50%) compared with the existing phase jump compensation methods. This enhancement can also be seen as a considerable reduction in dc link capacitor size for new installation. The performance of proposed method is evaluated using simulation study.

 

KEYWORDS:

  1. Dynamic voltage restorer (DVR)
  2. Voltage source inverter (VSI)
  3. Voltage sag compensation
  4. Voltage phase jump compensation.

 

SOFTWARE: MATLAB/SIMULINK

  

BLOCK DIAGRAM:

Fig. 1. Basic DVR based system configuration

 

EXPECTED SIMULATION RESULTS:

Fig. 2. Simulation results for the proposed sag compensation method for 50% sag depth. (a) PCC voltage, (b) load voltage, (c) DVR voltage, (d) DVR active and reactive power, and (e) dc link voltage.

Fig. 3. Simulation results for the proposed sag compensation method for 23% sag depth. (a) PCC voltage, (b) load voltage, (c) DVR voltage, (d) DVR active and reactive power, and (e) dc link voltage.

 

CONCLUSION

In this paper an enhanced sag compensation scheme is proposed for capacitor supported DVR. The proposed strategy improves the voltage quality of sensitive loads by protecting them against the grid voltage sags involving the phase jump. It also increases compensation time by operating in minimum active power mode through a controlled transition once the phase jump is compensated. To illustrate the effectiveness of the proposed method an analytical comparison is carried out with the existing phase jump compensation schemes. It is shown that compensation time can be extended from 10 to 25 cycles (considering pre sag injection as the reference method) for the designed limit of 50% sag depth with 450 phase jump. Further extension in compensation time can be achieved for intermediate sag depths. This extended compensation time can be seen as considerable reduction in dc link capacitor size (for the studied case more than 50%) for the new installation. The effectiveness of the proposed method is evaluated through extensive simulations in MATLAB/Simulink and validated on a scaled lab prototype experimentally. The experimental results demonstrate the feasibility of the proposed phase jump compensation method for practical applications.

 

REFERENCES

  • A. Martinez and J.M. Arnedo, “Voltage sag studies in distribution networks- part I: System modeling,” IEEE Trans. Power Del., vol. 21,no. 3, pp. 338–345, Jul. 2006.
  • G. Nielsen, F. Blaabjerg and N. Mohan, “Control strategies for dynamic voltage restorer, compensating voltage sags with phase jump,” in Proc. IEEE APEC, 2001, pp. 1267–1273.
  • D. Li, S.S. Choi, and D.M. Vilathgamuwa, “Impact of voltage phase jump on loads and its mitigation,” in Proc. 4th Int. Power Electron. Motion Control Conf., Xian, China, Aug. 14–16, 2004, vol. 3, pp. 1762– 176.
  • Sullivan, T. Vardell, and M. Johnson, “Power interruption costs to industrial and commercial consumers of electricity, IEEE Trans. Ind App., vol. 33, no. 6, pp. 1448–1458, Nov. 1997.
  • Kaniewski, Z. Fedyczak and G. Benysek “AC Voltage Sag/Swell Compensator Based on Three-Phase Hybrid Transformer With Buck- Boost Matrix-Reactance Chopper”, IEEE Trans. Ind. Electron., vol.61, issue. 8, Aug 2014.

 

Design and Performance Analysis of Three-Phase Solar PV Integrated UPQC

2016 IEEE

ABSTRACT: In this paper, the design and performance of a threephase solar PV (photovoltaic) integrated UPQC (PV-UPQC) are presented. The proposed system combines both the benefits of distributed generation and active power filtering. The shunt compensator of the PV-UPQC compensates for the load current harmonics and reactive power. The shunt compensator is also extracting maximum power from solar PV array by operating it at its maximum power point (MPP). The series compensator compensates for the grid side power quality problems such as grid voltage sags/swells by injecting appropriate voltage in phase with the grid voltage. The dynamic performance of the proposed system is simulated in Matlab-Simulink under a nonlinear load consisting of a bridge rectifier with voltage-fed load.

KEYWORDS:

  1. Power Quality
  2. DSTATCOM
  3. DVR
  4. UPQC
  5. Solar PV
  6. MPPT

SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

Fig. 1. System Configuration PV-UPQC

EXPECTED SIMULATION RESULTS:

 Fig. 2. Performance PV-UPQC at steady state condition

Fig. 3. PCC Voltage Harmonic Spectrum and THD

Fig. 4. Load Voltage Harmonic Spectrum and THD

Fig. 5. Load Current Harmonic Spectrum and THD

Fig. 6. Grid Current Harmonic Spectrum and THD

Fig. 7. Performance PV-UPQC at varying irradiation condition

Fig. 8. Performance of PV-UPQC under voltage sag and swell conditions

CONCLUSION:

The dynamic performance of three-phase PV-UPQC has been analyzed under conditions of variable irradiation and grid voltage sags/swells. It is observed that PV-UPQC mitigates the harmonics caused by nonlinear and maintains the THD of grid voltage, load voltage and grid current under limits of IEEE-519 standard. The system is found to be stable under variation of irradiation from 1000𝑊/𝑚2 to 600𝑊/𝑚2. It can be seen that PV-UPQC is a good solution for modern distribution system by integrating distributed generation with power quality improvement.

REFERENCES:

[1] Y. Yang, P. Enjeti, F. Blaabjerg, and H. Wang, “Wide-scale adoption of photovoltaic energy: Grid code modifications are explored in the distribution grid,” IEEE Ind. Appl. Mag., vol. 21, no. 5, pp. 21–31, Sept 2015.

[2] B. Singh, A. Chandra and K. A. Haddad, Power Quality: Problems and Mitigation Techniques. London: Wiley, 2015.

[3] M. Bollen and I. Guo, Signal Processing of Power Quality Disturbances. Hoboken: Johm Wiley, 2006.

[4] P. Jayaprakash, B. Singh, D. Kothari, A. Chandra, and K. Al-Haddad, “Control of reduced-rating dynamic voltage restorer with a battery energy storage system,” IEEE Trans. Ind. Appl., vol. 50, no. 2, pp. 1295– 1303, March 2014.

[5] M. Badoni, A. Singh, and B. Singh, “Variable forgetting factor recursive least square control algorithm for DSTATCOM,” IEEE Trans. Power Del., vol. 30, no. 5, pp. 2353–2361, Oct 2015.

Comparative Simulation Results of DVR and D-STATCOM to Improve Voltage Quality in Distributed Power System

ABSTRACT:

This paper presents the comparative improvement of the voltage profile of the distributed power system using a Dynamic Voltage Restorer (DVR) and a Distributed Static Synchronous Compensator (D-STATCOM). The IEEE benchmark 13-bus distributed power system is used to present the distributed power grid. A proposed DVR is connected in series with bus 632 while a D-STATCOM is connected in parallel with bus 632. Comparative simulation results of the system with DVR and D-STATCOM are performed by using commercial MATLAB software. It can be concluded from the simulation results that DVR is suitable to mitigate the voltage sag of the load side while D-STATCOM can enhance the voltage stability margin of the buses that are located near the connected bus of the proposed D-STATCOM in the distributed grid.

 

KEYWORDS:

  1. Distributed Power System
  2. Dynamic Voltage Restorer (DVR)
  3. Distributed Static Synchronous Compensator (D-STATCOM)
  4. Voltage Quality.

 

SOFTWARE: MATLAB/SIMULINK

 

DVR AND STATCOM MODELS:

Figure 1. Basic DVR Model

Figure 2. Basic D-ST ATCOM Model

 

EXPECTED SIMULATION RESULTS:

Voltage at bus 633 without DVRlD-STATCOM

Voltage at bus 646 with D-STATCOM

Voltage at bus 633 with D-STATCOM

Voltage at bus 684 with D-STATCOM

Voltage at bus 646 with DVR

Voltage at bus 633 with DVR

Voltage at bus 684 with DVR

Figure 3. Simulation results of the studied system when a three-phase short-circuit fault happened at bus 633.

 

CONCLUSION:

In this paper, the voltage stability improvement of an IEEE I3-bus distributed power system has been presented. A DVR and a D-STATCOM have been proposed and integrated to the studied system. Based on the results from the simulation, it can be concluded that the proposed DSTATCOM is better than DVR for improving the voltage quality of the distributed power system under a severe fault happened.

 

 REFERENCES:

  • Bollen, “Understanding Power Quality Problems – Voltage Sags and Interruptions”, IEEE Press Series on Power Engineering – John Wiley and Sons, Piscataway, USA, 2000.
  • Math H.J. Bollen, Understanding power quality problems: voltage sags and interruptions, IEEE Press, New York, 2000.
  • FACTS controllers in power transmission and distribution by K. R. Padiyar ISBN: 978-81-224-2541-3.
  • Singh, A. Adya, A. P. Mittal and J. R. P. Gupta, “Modeling, Design and Analysis of Different Controllers for DSTATCOM,” 2008 Joint International Conference on Power System Technology and IEEE Power india Conference, New Delhi, 2008, pp. 1-8.
  • Devaraju, V. C. Reddy and M. Vijaya Kumar, “Performance of DVR under different voltage sag and swell conditions”, ARPN Journal of Engineering and Applied Sciences, Vol. 5, No. 10,2010, pp. 56-64.

Verification of New Family for Cascade Multilevel Inverters with Reduction of Components

 

ABSTRACT:

This paper presents a new group for multilevel converter that operates as symmetric and asymmetric state. The proposed multilevel converter generates DC voltage levels similar to other topologies with less number of semiconductor switches. It results in the reduction of the number of switches, losses, installation area, and converter cost. To verify the voltage injection capabilities of the proposed inverter, the proposed topology is used in dynamic voltage restorer (DVR) to restore load voltage. The operation and performance of the proposed multilevel converters are verified by simulation using SIMULINK/MATLAB and experimental results.

 KEYWORDS:

  1. Cascaded multilevel converter,
  2. New topology
  3. Reduction of components
  4. DVR

 SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

 image001

Fig. 1. Proposed cascade topology
image002

 Fig. 2. Proposed topology with four DC voltage sources.

 EXPECTED SIMULATION RESULTS:

 image003

image004

image005

Fig. 3. (a) Supply voltage, (b) DVR injection voltage, and (c) load voltage for the three-phase balanced voltage sag.

image006

Fig. 4. Output phase voltage in fault (sag) time

image007

image008

image009

Fig. 5. (a) Supply voltage, (b) DVR injection voltage, and (c) load voltage for the three-phase balanced voltage swell.

image010

Fig. 6. Output phase voltage in fault (swell) time.

 CONCLUSION:

 In this paper, a novel topology was presented for multilevel converter, which has reduced number of switches. The suggested topology needs fewer switches for realizing voltages for the same levels of output voltages. This point reduces the installation area and the number of gate driver circuits. Therefore, the cost of the suggested topology is less than the conventional topology. Based on the presented switching algorithm, the multilevel inverter generates near sinusoidal output voltage, causing very low harmonic distortion. The suggested inverter used in DVR does not require any coupling series transformer and has lower cost, smaller size, and higher performance and efficiency. Simulation results verified the validity of the presented concept.

REFERENCES:

[1] Z. Pan, F.Z. Peng, “Harmonics optimization of the voltage balancing control for multilevel converter/ inverter systems”, IEEE Trans. Power Electronics, pp. 211-218, 2006.

[2] L.M. Tolbert, F. Z. Peng, T. Cunnyngham, J. N. Chiasson, “Charge Balance Control Schemes for Cascade Multilevel Converter in Hybrid Electric Vehicles,” IEEE Trans. Industrial Electronics, Vol. 49, No. 5, pp. 1058-1064, Oct. 2002.

[3] S. Mariethoz, A. Rufer, “New configurations for the three-phase asymmetrical multilevel inverter,” in Proceeding of the IEEE 39th Annual Industry Applications Conference, pp. 828-835, Oct. 2004.

[4] J.Rodriguez, J.S. Lai, F.Z. Peng, “Multilevel Inverter: A Survey of Topologies, Controls, and applications”, IEEE Trans. on Industrial Electronics, Vol. 49, No. 4, August. 2002.

[5] J.S. Lai, F.Z. Peng, “Multilevel Converters-A New Breed of power Converters”, IEEE Trans. Industry Application, Vol. 32, No. 3, pp. 509-517, MAY/JUNE.1996