A Single-Phase Cascaded Multilevel Inverter Composed of Four-Level Sub-multilevel Cells

ABSTRACT

This paper presents a novel cascaded multilevel inverter topology. The series connection of proposed basic cells is the main core of this topology. Different methods to determine the values of DC voltage sources in cells are investigated. Advantages and disadvantages of this topology in comparison with classical topologies are discussed. Symmetric and asymmetric structures of this topology are well analyzed through simulations.

 KEYWORDS

  1. Cascaded multilevel inverter
  2. Single phase

 SOFTWARE: MATLAB/SIMULINK

 GENERAL SCHEMATIC CIRCUIT DIAGRAM:

Fig.. 1. General scheme of proposed cascaded multilevel inverter

EXPECTED SIMULATION RESULTS


Fig. 2. Simulation results of two-cell proposed inverter Symmetric design: (a) va (b) Vaal and iout(c) THD Asymmetric design: (d) va (e) Vout and iout(f) THD

Fig.3.The blocking voltage of  switches(a) S11 and S12 (b)S21 and  S22  (c)S31 and S32 (d)S41 and S42 (e) Sa (f) Sb  (g) T1 and T4 (h)  T2 and T3.

 CONCLUSION

In this paper a new structure for multilevel inverters based on series connection of four-level sub-multilevel basic cells is proposed. The H-bridge inverter and additional circuit have been added to the basic form of the proposed inverter in order to generate positive and negative polarities and facilitate the symmetric and asymmetric implementations regarding the values of the dc sources. Different methods are suggested to choose the values of the dc sources and they are appraised by comparison studies with classical cascaded H-bridge inverter. The results of this survey illustrate the fact that the number of switches and the total blocking voltage of the inverter are reduced for the proposed topology compared to the classical ones. Finally, the simulation results on a two-cell inverter with symmetric and asymmetric implementation confirm the proper performance of the proposed topology.

 REFERENCES

[I] 1. Franquelo, J. Rodriguez, J. Leon, S. Kouro, R. Portillo, and M. EPrlaectst,ro “nT. hMea ga.g, e of multilevel converters arrives,” IEEE Ind. vol. 2, no. 2, pp. 28-39, Jun. 2008.

[2] J. Rodriguez, S. Member, J. Lai, and S. Member, “Multilevel Inverters : A Survey of Topologies , Controls , and Applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738,2002.

[3] J. Rodriguez, 1. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications,” Proc. IEEE, vol. 97, no. II, pp. 1786-1817, Nov. 2009.

[4] J.-S. 1. J.-S. Lai and F. Z. P. F. Z. Peng, “Multilevel converters-a new breed of power converters,” lAS ’95. Coif. Rec. 1995 IEEE Ind. Appl. Can! Thirtieth lAS Annu. Meet., vol. 3, no. 3, pp. 509-517,1995.

[5] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, E”Ale cStruorvne.,y on Cascaded Multilevel Inverters,” IEEE Trans. Ind. vol. 57, no. 7, pp. 2197-2206, Jul. 2010.

 

Single-Stage Switched-Capacitor Module (S3CM) Topology for Cascaded Multilevel Inverter

ABSTRACT:

A two-stage switched-capacitor based multilevel inverter possesses a drawback such that switches in the second stage (i.e. H-bridge) endure higher voltage stress. To resolve this problem, this letter proposes a single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter which ensures the peak inverse voltage across all switches within the dc source voltage. Nine voltage levels can be generated with only one dc source and two incorporated capacitors. Hence, the number of isolated dc sources are significantly reduced compared to cascaded H-bridge. In addition, voltage boosting gain of two is achieved. A comparative analysis against the recent topology reveals that the proposed S3CM topology achieves switch count reduction. The operation of the proposed topology is validated through circuit analysis followed by experimental results of a single module (9-level) prototype.

 

KEYWORDS:

  1. Cascaded multilevel inverter
  2. Single-Stage Switched capacitor module
  3. Multilevel inverter

 

SOFTWARE: MATLAB/SIMULINK

  

CIRCUIT DIAGRAM:

Fig. 1. The proposed single-stage switched-capacitor module (S3CM) topology for cascaded MLI.

 

EXPECTED SIMULATION RESULTS:

Fig. 2. Simulated steady-state waveforms for single S3CM (9-level).

Fig. 3 Simulated capacitor voltage considering 20% tolerances in capacitance.

Fig. 4. Simulated waveforms for step load change.

(a)

(b)

Fig. 5. Simulated waveforms with sinusoidal pulse width modulation (SPWM) for (a) purely resistive load, and (b) resistive-inductive load.

 

CONCLUSION:

In this letter, a 9-level inverter module based on single-stage switched-capacitor circuit is established for cascaded MLI. The proposed S3CM topology requires only single dc source with a voltage boosting gain of two. Circuit analysis demonstrated that the voltage stress across all switches are within the dc source voltage. Therefore, it is capable of generating more levels and higher voltages up to twice the dc source by using switches with low voltage rating. Comparative analysis against the recent SCM topology and the H-bridge for cascaded MLI validates its merits of reduced switch count as well as reduced dc source count. The performance of the proposed topology are convincingly validated via experiments, with all the results are in good agreement with theoretical analysis. The improvements of the proposed S3CM topology made it an attractive alternative for high-voltage dc-ac power conversion systems.

  

REFERENCES:

  • Akagi, “Multilevel Converters: Fundamental Circuits and Systems,” Proc.IEEE, vol. 105, no. 11, pp. 2048–2065, 2017.
  • K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel Inverter Topologies with Reduced Device Count: A Review,” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 135–151, 2016.
  • Samadaei, S. A. Gholamian, A. Sheikholeslami, and J. Adabi, “An Envelope Type (E-Type) Module: Asymmetric Multilevel Inverters With Reduced Components,” IEEE Trans. Ind. Electron., vol. 63, no. 11, pp. 7148–7156, 2016.
  • Samadaei, A. Sheikholeslami, S.-A. Gholamian, and J. Adabi, “A Square T-Type (ST-Type) Module for Asymmetrical Multilevel Inverters,” IEEE Trans. Power Electron., vol. 33, no. 2, pp. 987–996, 2018.
  • S. Alishah, S. H. Hosseini, E. Babaei, and M. Sabahi, “Optimal Design of New Cascaded Switch-Ladder Multilevel Inverter Structure,” IEEE Trans. Ind. Electron., vol. 64, no. 3, pp. 2072–2080, 2017.

Dynamic voltage restorer employing multilevel cascaded H-bridge inverter

IET Power Electronics, 2016

ABSTRACT: This study presents design and analysis of a dynamic voltage restorer (DVR) which employs a cascaded multilevel inverter with capacitors as energy sources. The multilevel inverter enables the DVR to connect directly to the medium voltage networks, hence, eliminating the series injection transformer. Using zero energy compensation method, the DVR does not need active energy storage systems, such as batteries. Since the energy storage system only includes capacitors, the control system will face some additional challenges compared with other DVR systems. Controlling the voltage of capacitors around a reference voltage and keeping the balance between them, in standby and compensation period, is one of them. A control scheme is presented in this study that overcomes the challenges. Additionally, a fast three-phase estimation method is employed to minimize the delay of DVR and to mitigate the voltage sags as fast as possible. Performance of the control scheme and estimation method is assessed using several simulations in MATLAB / SIMULINK environments.

KEYWORDS:

  1. Multilevel inverter
  2. cascaded H-bridge inverter
  3. Dynamic Voltage Restorer

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

 Multilevel inverter

 Fig. 1 DVR strcuctures  a) Conventional DVR b) CHB-based DVR

 EXPECTED SIMULATION RESULTS:

Fig. 2 Three-phase voltage sag a) Network voltage b) Injected voltage by the DVR c) Load-side voltage

 Fig. 3 Unbalanced voltage sag (a 20% voltage sag on phase A) a) Source voltage b) Injected voltage by the DVR c) Load-side voltage

Fig. 4 Voltages of the DC link capacitors

Fig. 5 Three-phase 20% voltage sag with voltage harmonics a) Network voltage b) Injected voltage by the DVR c) Load-side voltage

 

CONCLUSION:

This paper presented design and performance assessment of a DVR based on the voltage sag data collected from MWPI. Using a multilevel converter, the proposed DVR was capable of direct connection to the medium voltage-level network without a series injection transformer. In addition, development of zero active power compensation technique helps to achieve voltage restoration goal just by the capacitors as energy storages. Due to internal losses of H-bridge cells and probable inaccuracies in measurements, voltage of DC link capacitors may become unequal, which prevents proper operation of the converter. A voltage control scheme, comprised of three separate controllers, was proposed in this paper for keeping voltage balance among the DC link capacitors within nominal range. A fast estimation method was also employed for calculation of phase and magnitude terms in an unbalanced three-phase system. This estimation method is able to recognise voltage sags in approximately half a cycle. Several simulations were performed in PSCAD/EMTDC environment to verify the performance of CHB-based DVR. Additionally, a laboratory-scale prototype of the proposed DVR was built and tested. Results of the experimental test also confirmed validity of the proposed control system.

 REFERENCES:

1 Chapman, D.: ‘The cost of poor power quality’ (European Copper Institute, Copper Development Association, 2001), March

2 Radmehr, M., Farhangi, S., Nasiri, A.: ‘Effects of power quality distortions on electrical drives and transformer life in paper industries’, IEEE Ind. Appl. Mag., 2007, 13, (5), pp. 38–48

3 Lamoree, J., Mueller, D., Vinett, P.: ‘Voltage sag analysis case studies’, IEEE Trans. Ind. Appl., 1994, 30, (4), pp. 1083–1089

4 Bollen, M.H.J.: ‘Understanding power quality problems: voltage sags and interruptions’ (New York, Saranarce University of Technology, 2000)

5 Ghosh, A., Ledwich, G.: ‘Power quality enhancement using custom power devices’ (Berlin, Kluwer Academic Publications, 2002)

A Five Level Cascaded H-Bridge Multilevel STATCOM

2015, IEEE

ABSTRACT: This paper describes a three-phase cascade Static Synchronous Compensator (STATCOM) without transformer. Lt presents a control algorithm that meets the demand of load reactive power and also voltage balancing of isolated dc capacitors for H-bridges. The control algorithm used for inverter in this paper is based on a phase shifted carrier (PSC) modulation strategy that has no restriction on the cascaded number. The performance of the STATCOM for different changes of loads was simulated.

 KEYWORDS:

  1. STATCOM
  2. PSCPWM
  3. Cascaded Multilevel Inverter

 SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig1.cascaded multilevel STATCOM.

EXPECTED SIMULATION RESULTS:

 

Fig. 2 Source voltage, source current and inverter current far inductive load(sourece current gain-5 and Inverter current gain-8).

Fig. 3 Load & Inverter Reactive componenets of current for Inductive load.

F ig. 4 Response of DC link voltage for inductive load.

Fig. 5 Source voltage and inverter current for the change of inductive load to half of the load at I sec(lnverter current gain-8)

Fig. 6 Load & Inverter Reactive componenets of current for the change of Inductive load to half of the load at I sec.

Fig. 7 Source voltage and inverter current for the change of inductive load to standby at 1 sec (Inverter current gain-8).

Fig. 8 Load & Inverter Reactive componenets of current for the change of Inductive load to standby at 1 sec

F ig. 9 Inverter Output Voltage

Fig. 10 Harmonie spectrum ofInverter line voltage.

Fig. 11 Load & Inverter reactive component for the change of Inductive to

capacitive load at 1.5 Sec.

Fig. 12 Response of oe link voltage for change in mode of operation from

inductive to capacitive load at 1.5 Sec.

Fig. 13 Inverter reactive component for the change of Inductive to capacitive load at 2 Sec

Fig. 14 Response of OC link voltage for change in mode of operation from inductive to capacitive at 2 Sec

CONCLUSION:

The cascaded H-bridge multilevel topology is used as one of the more suitable topologies for reactive-power compensation applications. This paper presents a new control strategy for cascaded H-bridge multilevel converter based STATCOM. By this control strategy, the dc-link voltage of the inverter is controlled at their respective values when the ST A TCOM mode is converted from inductive to capacitive. The dc link voltages of the inverter are kept balanced in all the circumstances, and the reactive power that is produced by the STATCOM is equally distributed among all the H-bridges.

REFERENCES:

[1] N. N. V. Surendra Babu, and B.G. Fernandes, ” Cascaded Two Level Inverter- Based Multilevel ST ATCOM for High-Power Applications,” IEEEE Trans. Power Delivery., vol. 29, no. 3, pp. 993-1001, lune. 2014.

[2] N.G. Hingorani and L. Gyagyi, “Understanding F ACTS”, Delhi, India: IEEE, 2001, Standard publishers distributors.

[3] B. Singh, R. Saha, A. Chandra, and K. AI- Haddad, ” Static synchronous compensators (ST A TCOM): A review, ” lET Power Electron., vol. 2, no. 4, pp. 297-324, 2009.

[4] Hirofumi Akagi, Shigenori Inoue and Tsurugi Yoshii, “Control and Performance of a Transformerless Cascade PWM ST A TCOM With Star Contiguration,” IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. 1041-1049, July/ August 2007.

[5] H. Akagi, H. Fujita, S.Yonetaniand Y. Kondo, “A 6.6-kV transformerless ST ATCOM based on a tivelevel diode-clamped PWM converter: System design and experimentation of a 200-V 1 O-kV A laboratory model,” IEEE Trans. Ind. Appl., vol. 44, no. 2, pp. 672-680, Mar./Apr. 2008.