Investigation on cascade multilevel inverter with symmetric, asymmetric, hybrid and multi-cell configurations

ABSTRACT:  

In recent past, numerous multilevel architectures came into existence but in this background, cascaded multilevel invert er (CM LI) is the promising structure. This type of multilevel invert er s synthesizes a medium voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltage and current wave forms, however, when the number of levels increases switching components and the count of dc sources are also increased.

This issue became a key motivation for the present paper which is devoted to investigate different types of CM LI using less number of switching components and dc sources thus finally proposed a new version of Multi-cell based CM LI. In order to verify the proposed topology, MAT LAB – simulations and hardware verification are carried out and results are presented.

KEYWORDS:
  1. Cascade multilevel invert er
  2. Multi-cell
  3. Switching components
  4. High quality output voltages

 SOFTWARE: MAT LAB/SIM U LINK

 INVESTIGATION ON CASCADE MULTILEVEL INVERT ER:

Figure 1 (a) CH B multilevel invert er, (b) key waveform for seven-level invert er, (c) CH B multilevel invert er by employing single-phase transformers, (d) simulation verification of seven-level CH B multilevel invert er, (e) F  FT spectrum.

 

Figure 2 (a) Asymmetrical thirteen-level CH B invert er, (b) simulation verification of thirteen-level CH B multilevel invert er, (c) FF T spectrum.

 

Figure 3 (a) Asymmetrical CH B multilevel invert er, (b) output voltages of each H-bridge module, (c) twenty-seven level output voltage waveform, (d) F FT spectrum.

 

Figure 4 (a) Asymmetrical CH B multilevel invert er using sub-cells, (b) output voltage of sub-cells, (c) thirty-one level output voltage waveform, (d) FF T spectrum.

 

Figure 5 (a) Hybrid CH B multilevel invert er, (b) output voltage of each H-bridge and load voltage (nine-level) waveform, (c) FF T spectrum.

Figure 6 (a) Hybrid multilevel invert er using traditional invert er, (b) output voltage waveform, (c) FF T Spectrum.

 

Figure 7 The proposed multi-cell CM LI.

.Figure 8 (a) The proposed 25-level asymmetric multi-cell CM LI, (b) key wave forms.

Figure 9 (a) Output voltage of first H-bridge, (b) output voltage of second H-bridge, (c) resultant output voltage with 25-levels, (d) FF T spectrum.

 CONCLUSION:

 In this paper CM LI with sub-cells is proposed with less number of switches. To highlight the merits of proposed invert er, an in-depth investigation is carried out on symmetric, asymmetric and hybrid multilevel invert er s based on CH B top o log i es. Symmetric configuration has capacity to produce only limited number of levels in output voltage, On the counter side, symmetrical configuration can be operated in asymmetrical mode with different DC sources. However, asymmetrical configurations can produce higher number of output levels and thereby qualitative output wave forms could be generated.

Later,

hybrid CH B invert er s are also introduced, which utilizes single DC source for entire structure. Thus complexity and voltage balancing issues can be reduced. Finally proposed invert er is introduced with less number of switching components and able to produce qualitative output wave forms. To verify the proposed invert er adequate simulation is done with help of MAT LAB/sim u link. Later on, hardware variations are carried out in laboratory. Verification are quite impressive with greater number of levels in the output voltage and lower harmonic content in FF T spectrum s. Spectrum s indicate that, low order harmonics are drastically reduced. Thus power quality is significantly enhanced. Thus proposed invert er shows some promising attributes when compared with traditional CH B based architectures.

References

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multilevel invert er s with reduced number of components based on
developed H-bridge. IEEE Trans Ind Electron 2014;61(8):3932–9.
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[4] K ho u c ha Far id, Lag o  n M o u n a So um i a, K he l o i Ab d e l a z i z,
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A Single DC Source Cascaded Seven-Level Inverter Integrating Switched Capacitor Techniques

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2015

ABSTRACT: In this paper, a novel cascaded seven-level inverter topology with a single input source integrating switched capacitor techniques is presented. Compared with the traditional cascade multilevel inverter (CMI), the proposed topology replaces all the separate dc sources with capacitors, leaving only one H-bridge cell with a real dc voltage source and only adds two charging switches. The capacitor charging circuit contains only power switches, so that the capacitor charging time is independent of the load. The capacitor voltage can be controlled at a desired level without complex voltage control algorithm and only use the most common carrier phase-shifted sinusoidal pulse width modulation (CPS-SPWM) strategy. The operation principle and the charging-discharging characteristic analysis are discussed in detail. A 1kW experimental prototype is built and tested to verify the feasibility and effectiveness of the proposed topology.

KEYWORDS:

  1. Cascaded seven-level inverter
  2. Switched capacitor techniques
  3. Carrier phase-shifted sinusoidal pulse width modulation
  4. Charging and discharging characteristic

 SOFTWARE: MATLAB/SIMULINK

CONTROL DIAGRAM:

Fig. 1. Topologies of the proposed inverter. (a) The novel single dc source cascaded seven-level inverter. (b) Three-input cascaded seven-level inverter for PV systems.

EXPECTED SIMULATION RESULTS:

 Fig. 2. Output voltage and current waveforms. (a) At resistive load. (b) At inductive load. (c) THD value of the output voltage

Fig. 3. Voltage waveforms of the charging-switch. (a) SC1. (b) SC3.

Fig. 4. The capacitor voltage and the charging current waveforms of capacitors C1. (a) RESR=5mΩ. (b) RESR=200mΩ.

 CONCLUSION:

A novel single DC source cascaded seven-level inverter integrating switched capacitor techniques is developed in this paper. In the proposed topology, the transformerless charging circuit only contains power switches and capacitors, and the charging time is independent of the load. The operation principle and the charging-discharging characteristic analysis are investigated in depth. With the common CPS-SPWM strategy, the sinusoidal output voltage can be well obtained. Moreover, the capacitors are properly charged without complex voltage balancing control algorithm. The peak charging current and the charging loss can be reduced with appropriate circuit parameters. The proposed topology has the features of modularity, low cost and simplicity of control and makes it attractive in DC-AC power applications. A 1Kw experimental prototype verifies the feasibility of the proposed inverter. The proposed inverter is also suitable for photovoltaic-battery multi-input application with high redundancy.

 REFERENCES:

[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron. , vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[2] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, “Medium-voltage multilevel converters; state of the art, challenges, and requirements in industrial applications,” IEEE Trans. Ind. Electron. , vol. 57, no. 8, pp. 2581–2596, Aug. 2010.

[3] J. Dixon, J. Pereda, C. Castillo, and S. Bosch, “Asymmetrical multilevel inverter for traction drives using only one dc supply,” IEEE Trans. Veh. Technol., vol. 59, no. 8, pp. 3736–3743, Oct. 2010.

[4] S. Lu, K. A. Corzine, and M. Ferdowsi, “A unique ultracapacitor direct integration scheme in multilevel motor drives for large vehicle propulsion,” IEEE Trans. Veh. Technol., vol. 56, no. 4, pp. 1506–1515, Jul. 2007.

[5] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A survey on neutral-point-clamped inverters,” IEEE Trans. Ind. Electron. , vol. 57, no. 7, pp. 2219–2230, Jul. 2010.