Novel High Efficiency High Voltage Gain Topologies for AC-DC Conversion with Power Factor Correction for Elevator Systems


This paper proposed Novel power factor corrected ac dc rectifier typologies suitable for induction motor drive based elevator application. These converters make use of coupled induct or for power conversion and are capable of providing high voltage gain at low duty cycle and high efficiency. Feedback control loop controls the current flowing through the coupled induct or to achieve unity power factor. The TH D value of the current i approximately 4.8 % which is within the limits prescribed by various standards.


the use of coupled induct or, the voltage stress of the switches operating at high frequency is reduced, which reduces switching losses. The loss comparison with the conventional converters shows a reduction of at least 22 % of losses. The proposed scheme also results in reduction of the variable frequency drive’s dc link capacitance value.  As an ultra capacitor bank is interfaced with the dc link through a bidirectional converter for improving efficiency and providing transient power requirements. This also helps in increasing the reliability and dynamic response of the system. The settling time for a step change in voltage reference is reduced by nearly 50%. MAT LAB/Sim u link simulations validates the proposed typologies and schemes.


 Fig. 1 Block diagram of an elevator system


 Fig. 2(a) Input current and voltage of the proposed 1 p h rectifier system with PFC; (b)3 p h current for PFC operation of proposed rectifier configuration; (c) The dc link voltage step changes for 10μF and 500μF dc link capacitor; and (d) Ultra capacitor current.


Simulation studies proposed, analyzed and validated the Novel AC DC PW M rectifier typologies for 1 p h and 3 p h systems, based on high voltage gain dc dc converter principle. A major advantage of these typologies is that it is possible to achieve higher voltage gain at lower duty ratio. This paper maintained operation symmetry  and achieved the Input power factor correction. The use of coupled induct or s enhances gain, but it also increases the ripple in the input current as there is an increase in turns ratio. Thus, there is a trade off between the achievable gain and the ripple.


The losses of the proposed converter are compared with the conventional ac dc converter, and observed the reduction of about 22% losses. The losses estimated through experimental studies also reduced from 29 W to 24 W with the use  of proposed topology . This shows a reduction of 17% losses in experiments. Therefore, the proposed converter gives higher efficiency than the conventional ac-dc converters. And the use of an auxiliary storage reduced the dc link capacitance value from 500 μF to 10 μF for a 1 p h system. For the 3 p h system, the auxiliary unit is used as a support during the grid voltage sag condition thereby reducing the dc link capacitance requirement. A low value of dc link capacitance not only helps in reducing the size. And improving the reliability of system, also in improving the dynamic response of the system.


The paper presented the simulation results of the complete system . A detailed description of the thought process behind the development of the proposed converter is also presented. The same thought process is extended to the development of such converter typologies. The voltage stress on switch S 2 and S 3 reduces to 1 and 8th of its value as compared to the conventional topology. But, the value of peak current increases ‘n’ times. The increase in peak current increases the high frequency current ripple in the input side. However, the increase in the value of ‘n’ decreases the duty cycle. Therefore, increased the overall efficiency of the converter.


paper proposed the unidirectional ac dc typologies. But, they can be made bidirectional by connecting a controllable switch across the diodes. This scheme is useful for the scenarios where the loads are regenerating. These bidirectional typologies are used as dc ac converters to feed power into the grid. Thus, giving very wide and relevant scope of the proposed schemes.



[1] Ash o k B. K u l k a r n i, H e in Nguyen, E. W. Ga u d e t, “A Comparative Evaluation of Line Regenerative and Non- regenerative Vector Controlled Drives for AC Gear less Elevators” 35th I AS Annual Meeting and World Conference on Industrial Applications of Electrical Energy, Rome, Italy: Institute of Electrical and Electronics Engineers Inc., Pis cat away, NJ, Oct 2000, vol. 3.pp 1431 to 1437.

[2] “IEEE Std. 519”, IEEE Recommended Practices and Requirements for Harmonic Control in Electric Power Systems, 1992.

[3] “IE C 1000 3 2 Int. Std.”, Limits for Harmonics Current Emissions (Equipment Input Cur rent 16 A per Phase), 1995.

[4] “IE C 61000 3 4”, Limitations of Emission of Harmonic Current in Low- Voltage Power Supply Systems for Equipment with Rated Current Greater than 16 A, 1998.

[5] J. Hahn, P. N. En jet i and I. J. Pit e l, “A new three-phase power-factor correction (PFC) scheme using two single-phase PFC modules,” in IEEE Transactions on Industry Applications, vol. 38, no. 1, pp. 123-130, Jan/Feb 2002.


[6]Hen g ch u n Mao, C. Y. Lee, D. B o r o ye vi ch and S. Hit i, “Review of high performance three-phase power-factor correction circuits,” in IEEE
Transactions on Industrial Electronics, vol. 44, no. 4, pp. 437-446, Aug 1997.
[7] Y u n g ta e k Jan g and M. M. Jo v a n o v i c, “A comparative study of singles witch three-phase high-power-factor rectifiers,” IEEE Transactions on Industry Applications, vol. 34, no. 6, pp. 1327-1334, Nov/Dec 1998.
[8] M. M. Cameron, “Trends in power factor correction with harmonic filtering,” in IEEE Transactions on Industry Applications, vol. 29, no. 1, pp. 60-65, Jan/Feb 1993.
[9] C. L. Cooper, R. O. Pr  a g ale and T. J. Di o n i s e, “A Systematic Approach for Medium-Voltage Power Factor Correction Design,” IEEE Transactions on Industry Applications, vol. 49, no. 3, pp. 1043-1055, May-June 2013.

A Multi-Input Bridgeless Resonant AC-DC Converter for Electromagnetic Energy Harvesting


In this paper, a novel high development up dc/dc converter is shown for reasonable power source applications. The proposed structure includes a coupled inductor and two voltage multiplier cells, in order to get high development up voltage gain. In addition, two capacitors are charged in the midst of the kill time frame, using the essentialness set away in the coupled inductor which assembles the voltage trade gain. The imperativeness set away in the spillage inductance is reused with the usage of an inactive catch circuit. The voltage load on the key power switch is also diminished in the proposed topology. In this manner, an essential influence switch with low restriction RDS(ON) can be used to diminish the conduction adversities. The action rule and the persevering state examinations are discussed by and large. To check the execution of the showed converter, a 300-W lab demonstrate circuit is completed. The results favor the speculative examinations and the practicability of the displayed high development up converter.




Fig. 1. Multi-channel EMR generators and PEI system: (a) conventional PEI; and (b) proposed multi-input PEI.



Fig. 2. Illustrative scheme of the proposed multi-input converter (v(i)emf: EMF of #i reed; r(i)EMR: coil resistance; L(i)EMR: self-inductance; i(i)EMR: reed terminal current; v(i)EMR: reed terminal voltage; C(i)r1= C(i)r2: resonant capacitors; Lr: resonant inductor; Q(i)r1, Q(i)r2: MOSFETs; Dr: output diode; Co: output capacitor).



  •                                                             (a)
  • image005                                                                    (b)

Fig. 3. Experimental waveforms of power amplifiers: fin = 20 Hz; X-axis: 10 ms/div; Y-axis: (a) vemf = 3 Vrms; Ch1 = output voltage (Vo), 2.5 V/div; Ch2 = terminal voltage (vEMR) of reed #1, 10 V/div; Ch3 = input current (iEMR) of six reeds, 50 mA/div; and (b) vemf = 0.5 Vrms; Ch1 = output voltage (Vo), 0.5 V/div; Ch2 = terminal voltage (vEMR) of reed #1, 5 V/div; Ch3 = sum of the input currents (iEMR) of six reeds, 10 mA/div.

 image006                                                         (a)


  •                                                           (b)

Fig. 4. Experimental waveforms of power amplifiers with step change: X-axis: 40 ms/div; Y-axis: (a) vemf = from 1 Vrms to 2 Vrms; Ch1 = output voltage (Vo), 1 V/div; Ch2 = terminal voltage (vEMR) of reed #1, 5 V/div; Ch3 = input current (iEMR) of six reeds, 50 mA/div; and (b) fin = from 20 Hz to 50 Hz; Ch1 = output voltage (Vo), 0.5 V/div; Ch2 = terminal voltage (vEMR) of reed #1, 5 V/div; Ch3 = input current (iEMR) of six reeds, 50 mA/div.




  •                                                                 (b)

Fig. 5. Experimental waveforms of EMR generators: X-axis: (a) 20 ms/div; (b) 100 ms/div; Y-axis: (a) constant wind speed; (b) wind speed step change; Ch1 = terminal voltage (vEMR) of reed #2, 5 V/div; Ch2 = output voltage (Vo), 1 V/div; Ch3 = terminal voltage (vEMR) of reed #1, 10 V/div; Ch4 = input current (iEMR) of reed #1, 10 mA/div.


In this paper, a novel high advancement up dc/dc converter is appeared sensible power source applications.

The proposed structure incorporates a coupled inductor and two voltage multiplier cells, so as to get high improvement up voltage gain.

Moreover, two capacitors are charged amidst the kill time allotment, utilizing the vitality set away in the coupled inductor which collects the voltage exchange gain.

The significance set away in the spillage inductance is reused with the utilization of an inert catch circuit. The voltage stack on the key power switch is additionally reduced in the proposed topology. As such, a fundamental impact switch with low limitation RDS(ON) can be utilized to lessen the conduction misfortunes. The activity rule and the enduring state examinations are talked about all things considered. To check the execution of the indicated converter, a 300-W lab show circuit is finished. The outcomes support the theoretical examinations and the practicability of the showed high improvement up converter.