Implementation and Comparison of Symmetric and Asymmetric Multilevel Inverters for Dynamic Loads

ABSTRACT:

This paper implements and compares a symmetric hybridized cascaded multilevel inverter and an asymmetric multilevel inverter utilizing a switched capacitor unit for 17 level inverters. The symmetric hybridized multilevel inverter topology consists of a modified H-bridge inverter, which results in an increase in the output voltage to five level from the three level by using a bi-directional switch at the midpoint of a dual-input dc source. In the proposed asymmetric multilevel inverter, dc sources are replaced with the switched capacitor unit, which in turn boosts the output voltage and produces twice the voltage levels at the loads. The proposed topology with the staircase modulation technique has been verified using MATLAB_SIMULINK, and the results are experimentally executed with prototype models, which are interfaced with dSPACE RTI 1104. The results of the proposed topologies are experimentally obtained for steady state, and the performance of the same is tested under different resistive and inductive load disturbance conditions. The results substantiate that these multilevel inverter topologies are better stabilized during load disturbance conditions with low total harmonic distortion, a lesser number of switches, and increased output voltage levels, and these topologies well suit for renewable energy applications.

 

KEYWORDS:

  1. Multilevel inverter (MLI)
  2. Staircase pulse width modulation technique (SPWM)
  3. Switched capacitor unit (SCU)

SOFTWARE: MATLAB/SIMULINK

 

BLOCK DIAGRAM:

Fig. 1. Proposed 17-level symmetric MLI.

asymmetric Switched Capacitor MLI.

Fig. 2. Proposed 17-level asymmetric Switched Capacitor MLI.

 

EXPECTED SIMULATION RESULTS:

 17-level symmetric MLI.

Fig. 3. Individual stage output voltages, output voltage and current of 17-level symmetric MLI.

 

Fig. 4. Waveforms of proposed switched capacitor unit topology.

 

Fig. 5. (a). Waveforms of proposed switched capacitor unit 1 for 17 level MLI. (b). Waveforms of proposed switched capacitor unit 2 for 17 level MLI. (c). Output voltage and current waveforms of 17-level asymmetric Switched Capacitor MLI.

Fig. 6. Steady-state voltage and current response of 17 level symmetric inverter with a resistive load.

Fig. 7. Steady-state voltage and current response of 17 level Symmetric inverter with inductive load.

Fig. 8 Unity power factor to lagging power factor load disturbance response of 17 level symmetric inverter.

Fig. 9. Lagging power factor to unity power factor load disturbance response of 17 level symmetric inverter.

Fig. 10. Steady state voltage and current response of 17 level asymmetric inverter with resistive load.

 

Fig. 11. Steady-state voltage and current response of 17 level asymmetric inverter with inductive load.

Fig. 12. Unity power factor to lagging power factor load disturbance response of 17 level asymmetric inverter.

Fig. 13. Lagging power factor to unity power factor load disturbance response of 17 level asymmetric inverter.

 

CONCLUSION:

This research presents the implementation and analysis of a 17 level symmetric and asymmetric multilevel inverters. The proposed 17 level inverter systems have been effectively tested with unity and lagging power factor loads. In case A, testing has been carried out under steady-state condition, load disturbance conditions and analysis of THD with 17 level symmetric inverter output were presented. It is inferred from case A results that the system is readily adaptive and maintains a stable output voltage with 5.41 % THD for the aforesaid conditions while in case B, a THD with 4.54 % has been achieved, which is on par with IEEE standards. During load disturbances, the proposed topology is suitable for sudden load variant applications also. Due to low THD, these topologies inherently utilize a lesser number of switches and a minimum number of dc input voltage sources; hence, the volume density of the proposed inverter is observed to have improved. From case A and B results it can be inferred that the proposed topology multilevel inverters are suitable for renewable energy-fed applications.

 

REFERENCES:

  • Rodríguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724_738, Aug. 2002.
  • Babaei, S. Laali, and S. Alilu, “Cascaded multilevel inverter with series connection of novel H-bridge basic units,” IEEE Trans. Ind. Electron., vol. 61, no. 12, pp. 6664_6671, Dec. 2014.
  • Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications,” IEEE Trans. Power Electron., vol. 26, no. 11, pp. 3109_3118, Nov. 2011.
  • P. Reddy, M. R. A, M. Sahoo, and S. Keerthipat, “A fault tolerant multilevel inverter for improving the performance of pole-phase modulated nine-phase induction motor drive,” IEEE Trans. Ind. Electron., to be published, doi: 10.1109/TIE.2017.2733474.
  • M. Basri1 and S. Mekhile, “Digital predictive current control of multilevel four-leg voltage-source inverter under balanced and unbalanced load conditions,” IET Electr. Power Appl., vol. 11, no. 8, pp. 1499_1508, 2017.

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