Single-Stage Switched-Capacitor Module (S3CM) Topology for Cascaded Multilevel Inverter

ABSTRACT:

A two-stage switched-capacitor based multilevel inverter possesses a drawback such that switches in the second stage (i.e. H-bridge) endure higher voltage stress. To resolve this problem, this letter proposes a single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter which ensures the peak inverse voltage across all switches within the dc source voltage. Nine voltage levels can be generated with only one dc source and two incorporated capacitors. Hence, the number of isolated dc sources are significantly reduced compared to cascaded H-bridge. In addition, voltage boosting gain of two is achieved. A comparative analysis against the recent topology reveals that the proposed S3CM topology achieves switch count reduction. The operation of the proposed topology is validated through circuit analysis followed by experimental results of a single module (9-level) prototype.

 

KEYWORDS:

  1. Cascaded multilevel inverter
  2. Single-Stage Switched capacitor module
  3. Multilevel inverter

 

SOFTWARE: MATLAB/SIMULINK

  

CIRCUIT DIAGRAM:

Fig. 1. The proposed single-stage switched-capacitor module (S3CM) topology for cascaded MLI.

 

EXPECTED SIMULATION RESULTS:

Fig. 2. Simulated steady-state waveforms for single S3CM (9-level).

Fig. 3 Simulated capacitor voltage considering 20% tolerances in capacitance.

Fig. 4. Simulated waveforms for step load change.

(a)

(b)

Fig. 5. Simulated waveforms with sinusoidal pulse width modulation (SPWM) for (a) purely resistive load, and (b) resistive-inductive load.

 

CONCLUSION:

In this letter, a 9-level inverter module based on single-stage switched-capacitor circuit is established for cascaded MLI. The proposed S3CM topology requires only single dc source with a voltage boosting gain of two. Circuit analysis demonstrated that the voltage stress across all switches are within the dc source voltage. Therefore, it is capable of generating more levels and higher voltages up to twice the dc source by using switches with low voltage rating. Comparative analysis against the recent SCM topology and the H-bridge for cascaded MLI validates its merits of reduced switch count as well as reduced dc source count. The performance of the proposed topology are convincingly validated via experiments, with all the results are in good agreement with theoretical analysis. The improvements of the proposed S3CM topology made it an attractive alternative for high-voltage dc-ac power conversion systems.

  

REFERENCES:

  • Akagi, “Multilevel Converters: Fundamental Circuits and Systems,” Proc.IEEE, vol. 105, no. 11, pp. 2048–2065, 2017.
  • K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel Inverter Topologies with Reduced Device Count: A Review,” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 135–151, 2016.
  • Samadaei, S. A. Gholamian, A. Sheikholeslami, and J. Adabi, “An Envelope Type (E-Type) Module: Asymmetric Multilevel Inverters With Reduced Components,” IEEE Trans. Ind. Electron., vol. 63, no. 11, pp. 7148–7156, 2016.
  • Samadaei, A. Sheikholeslami, S.-A. Gholamian, and J. Adabi, “A Square T-Type (ST-Type) Module for Asymmetrical Multilevel Inverters,” IEEE Trans. Power Electron., vol. 33, no. 2, pp. 987–996, 2018.
  • S. Alishah, S. H. Hosseini, E. Babaei, and M. Sabahi, “Optimal Design of New Cascaded Switch-Ladder Multilevel Inverter Structure,” IEEE Trans. Ind. Electron., vol. 64, no. 3, pp. 2072–2080, 2017.

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