This paper proposes the combination of a novel modified quasi-Z-source (MqZS) inverter with a single-phase symmetrical hybrid three-level inverter in order to boost the inverter three-level output voltage. The proposed single-phase MqZS hybrid three-level inverter provides a higher boost ability and reduces the number of inductors in the source impedance, compared with both the single-phase three-level neural-point clamped (NPC) qZSI and the single-phase quasi-Z source cascaded multilevel inverter (CMI). Additionally, it can be extended to obtain the nine-level output voltage by cascading two three-level PWM switching cells with a separate MqZS and dc source, which herein is called a single-phase MqZS cascaded hybrid five-level inverter (MqZS-CHI). A modified modulation technique based on an alternative phase opposition disposition (APOD) scheme is suggested to effectively control the shoot-through state for boosting the dc-link voltage and balancing the two series capacitor voltages of the MqZS. The performances of both the proposed MqZS-CHI and the modulation techniques are verified through simulation and experimental results.
Fig. 1. The single-phase modified quasi-Z-source cascaded hybrid five- level inverter.
EXPECTED SIMULATION RESULTS:
Fig. 2 Simulation results of the proposed MqZS-CHI when M = 0.8 and D = 0.2; (a) ac output and dc-link voltages, output and dc-link voltages of cell 1 and the ac output voltage, (b) carrier signals, shoot-through signal, reference signal, two inductor currents, dc-link and capacitor voltages of cell 1.
Fig. 3. Simulation results of the proposed inverter when M = 0.7, D = 0.25: (a) switching frequency = 10 kHz, (b) switching frequency = 3 kHz.
This paper proposed two novel topologies for a single-phase MqZS hybrid three-level inverter and a single-phase MqZS-CHI designed by cascading two three-level PWM switching cells in order to obtain the output voltage with nine voltage levels. Compared with both the three-level NPC qZSI and the three-level qZS-CMI, the proposed MqZS hybrid three-level inverter reduces the number of inductors by two. Its boost factor is higher by a factor of two relative to that of the NPC qZSI, although dc source current is discontinuous. The proposed topology can produce a nine-level output voltage, which only requires nine high-frequency switching devices and four low-frequency switching devices in the SPFB. However, the voltage stress across the four low-frequency switches is twice or four times higher than that of the high-frequency switches. On the other hand, the four switches in the SPFB can be implemented with the low-frequency high-voltage switching devices, and the switching loss can be reduced. Through the simulation and experimental results, the dc-link voltage of each cell is boosted by 2.8 times, and an output voltage of 155 Vrms can be obtained from a 50 V dc input voltage at the low shoot-through duty ratio as 0.2. The THD of the filtered ac output voltages with the four different voltage levels ranges from 2.49 % to 3.6 %. The proposed modulation technique offers a simple implementation, and the balance of the two series capacitor voltages of the three-level PWM switching cell can be achieved.
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