This paper proposes a new single-phase inverter topology and describes the control method for the proposed inverter. The inverter consists of an energy buffer circuit, a dc-dc conversion circuit and an H-bridge circuit. The energy buffer circuit and H-bridge circuit enable the proposed inverter to output a multilevel voltage according to the proposed pulse width modulation (PWM) technique. The dc-dc conversion circuit can charge the buffer capacitor continuously because the dc-dc conversion control cooperates with the PWM. Simulation results confirm that the proposed inverter can reduce the voltage harmonics in the output and the dc-dc conversion current in comparison to a conventional inverter consisting of a dc-dc conversion circuit and H-bridge circuit. Experiments demonstrate that the proposed inverter can output currents of low total harmonic distortion and have higher efficiency than the conventional inverter. In addition, it is confirmed that these features of the proposed inverter contribute to the suppression of the circuit volume in spite of the increase in the number of devices in the circuit.
- Energy buffer circuit
- Single-phase inverter
- Dc-dc conversion
- Pulse width modulation
Fig. 1 Configuration of proposed inverter.
EXPECTED SIMULATION RESULTS:
Fig. 2 Waveforms for (a) proposed inverter and (b) conventional inverter during dc-ac conversion under conditions of Pac = 500 W, vs = 90 V, vb = 70 V and dc link command voltage vdcc = 160 V. (The scales for vg, vb, vdc and vo are 80 V/div., and those for ic and io are 4.0 A/div.)
Fig. 3 Waveforms of (a) proposed inverter and (b) conventional inverter during ac-dc conversion under conditions of Pdc = 500 W, vs = 90 V, vbc = 70 V and vdcc = 160 V. (The scales for vg, vb, vdc and vo are 80 V/div., and those for ic and io are 4.0 A/div.)
Fig. 4 Simulated waveforms of (a) proposed inverter and (b) MEB inverter with a buffer capacitance of 1 mF during dc-ac conversion under conditions of Pac = 500 W, vs = 90 V and vbc = 70 V. (The scales for vg, vb and vo are 80 V/div., and those for ic and io are 4.0 A/div.)
In this paper the most common multilevel inverter topologies were scrutinized to find the more appropriate topology for BESS application. The investigation has been done entitled of quantitative and qualitative studies. The important output parameters of inverter topologies were investigated as quantitative study, while other features such as reliability, modularity and functionality were scrutinized in qualitative study. Also, various inverter topologies have been evaluated in terms of required capacity in the same operating point. The simulation results proved that the ideal BESS power conversion system, among reviewed multi-level topologies, is Cascaded topology. This topology was chosen for three reasons. First, the efficiency and reliability studies were conducted, and the CMLI was found to be the most efficient and reliable topology with minimum amount of power loss compared to other topologies. Second, it subdivides the battery string and increases the high voltage functionality. Finally, capacitor volume, cost and THD studies were again confirmed the effectiveness of this topology in battery energy storage systems.
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