This paper proposes a new single-phase invert er topology and describes the control method for the proposed invert er. The invert er consists of an energy buffer circuit, a dc-dc conversion circuit and an H-bridge circuit. The energy buffer circuit and H-bridge circuit enable the proposed invert er to output a multilevel voltage according to the proposed pulse width modulation (P WM) technique. The dc-dc conversion circuit can charge the buffer capacitor continuously because the dc-dc conversion control cooperates with the P WM. Simulation results confirm that the proposed invert er can reduce the voltage harmonics in the output and the dc-dc conversion current in comparison to a conventional invert er consisting of a dc-dc conversion circuit and H-bridge circuit.
Simulation demonstrates that the proposed invert er can output currents of low total harmonic distortion and have higher efficiency than the conventional invert er. In addition, these features of the proposed invert er contribute to the suppression of the circuit volume in spite of the increase in the number of devices in the circuit.
SOFTWARE: MAT LAB/SIM U LINK
Fig. 1 Configuration of proposed invert er.
EXPECTED SIMULATION RESULTS:
Fig. 2 Wave forms for (a) proposed invert er and (b) conventional invert er during dc-ac conversion under conditions of P ac = 500 W, vs = 90 V, vb = 70 V and dc link command voltage v d cc = 160 V. (The scales for v g, vb, v dc and v o are 80 V/div., and those for i c and i o are 4.0 A/div.)
Fig. 3 Wave forms of (a) proposed invert er and (b) conventional invert er during ac-dc conversion under conditions of P dc = 500 W, vs = 90 V, v b c = 70 V and v d cc = 160 V. (The scales for v g, vb, v dc and v o are 80 V/div., and those for i c and i o are 4.0 A/div.)
Fig. 4 Simulated waveforms of (a) proposed inverter and (b) MEB inverter with a buffer capacitance of 1 mF during dc-ac conversion under conditions of Pac = 500 W, vs = 90 V and vbc = 70 V. (The scales for vg, vb and vo are 80 V/div., and those for ic and io are 4.0 A/div.)
In this paper the most common multilevel invert er top o lo g i es were scrutinized to find the more appropriate topology for BESS application. The investigation has been done entitled of quantitative and qualitative studies and the important output parameters of invert er top o l o g i es were investigated as quantitative study, while other features such as reliability, modular it y and functionality were scrutinized in qualitative study. Also, various invert er top o log i es have been evaluated in terms of required capacity in the same operating point. The simulation results proved that the ideal BESS power conversion system, among reviewed multi-level top o log i es, is Cascaded topology.
There are three reasons for choosing this topology, First, the efficiency and reliability studies were conducted, and the C M LI was found to be the most efficient and reliable topology with minimum amount of power loss compared to other top o log i es. Second, it subdivides the battery string and increases the high voltage functionality and Finally, capacitor volume, cost and TH D studies were again confirmed the effectiveness of this topology in battery energy storage systems.
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