**ABSTRACT**

This paper proposes another AC voltage sensorless control plot for three-stage beat width tweak rectifier. Another startup procedure to guarantee a smooth beginning of the framework is likewise proposed. The sensorless control conspire utilizes a versatile neural (AN) estimator embedded in voltage-arranged control to dispense with the matrix voltage sensors. The built up AN estimator joins a versatile neural system in arrangement with a versatile neural channel. The AN estimator structure prompts straightforward, precise and quick network voltages estimation, and makes it perfect for ease advanced flag processor execution. Lyapunov based security and parameters tuning of the AN estimator are performed. Reproduction and trial tests are completed to confirm the plausibility and adequacy of the AN estimator. Acquired outcomes demonstrate that; the proposed AN estimator exhibited quicker union and preferred exactness over the second request summed up integrator based estimator; the new startup technique maintained a strategic distance from the over-current and diminished the settling time; the AN estimator introduced superior exhibitions even under contorted and unequal matrix voltages.

**BLOCK DIAGRAM:**

Fig. 1. Overall structure of the developed AC voltage sensorless control.

**EXPECTED SIMULATION RESULTS**

Fig. 2. Steady-state performances of the AN estimator in diode rectifier operation mode (experiment): (a) computed input voltages *v**α**n *and *v**β**n*, (b) actual AC-line currents *i**α *and *i**β*, (c) actual grid voltage *e**α*, estimated grid voltage *e**α**,est *and estimation error and (d) actual grid voltage *e**β*, estimated grid voltage *e**β**,est *and estimation error.

Fig. 3. Steady-state performances of the PLL in diode rectifier operation mode (experiment): (a) computed *dq *components (*ed*, *eq*) with actual grid voltages and computed *dq *components (*ed,est*, *eq,est*) with estimated grid voltages and (b) computed angles *θ *and *θ**est *with actual and estimated grid voltages, respectively.

Fig. 4. Performances of the AN estimator at startup (experiment): (a) input voltages *v**α**n *and *v**β**n*, (b) actual AC-line currents *i**α *and *i**β*, (c) reference and measured DC-link voltages (*Vdc ref*, *Vdc*), (d) actual grid voltage *e**α*, estimated grid voltage *e**α**,est *and estimation error and (d) actual grid voltage *e**β*, estimated grid voltage *e**β**,est *and estimation error.

Fig. 5. Performances of the PLL at startup (experiment): (a) computed *dq *components (*ed*, *eq*) with actual grid voltages and computed *dq *components (*ed,est*, *eq,est*) with estimated grid voltages and (b) computed angles *θ *and *θ**est *with actual and estimated grid voltages, respectively.

Fig. 6. Transient performances of the AN estimator under *V*dc ref step change (experiment): (a) actual grid voltage *e**α*, estimated grid voltage *e**α**,est *and estimation error, (b) actual grid voltage *e**β*, estimated grid voltage *e**β**,est *and estimation error, (c) actual AC-line currents *i**α *and *i**β *and (d) reference and measured DC-link voltages.

Fig. 7. Transient performances of the PLL under *Vdc ref *step change (experiment): (a) computed *dq *components (*ed*, *eq*) with actual grid voltages and computed *dq *components (*ed,est*, *eq,est*) with estimated grid voltages and (b) computed angles *θ *and *θ**est *with actual and estimated grid voltages, respectively.

Fig. 8. Transient performances of the AN estimator under load resistance variation (experiment): (a) actual grid voltage *e**α*, estimated grid voltage *e**α**,est *and estimation error, (b) actual grid voltage *e**β*, estimated grid voltage *e**β**,est *and estimation error and (c) actual AC-line currents.

Fig. 9. Transient performances of the PLL under load resistance variation (experiment): (a) computed *dq *components (*ed*, *eq*) with actual grid voltages and computed *dq *components (*ed,est*, *eq,est*) with estimated grid voltages and (b) computed angles *θ *and *θ**est *with actual and estimated grid voltages, respectively.

Fig. 10. Transient performances of the AN estimator under symmetric grid voltages sag (experiment): (a) actual grid voltage *e**α*, estimated grid voltage *e**α**,est *and estimation error and (b) actual grid voltage *e**β*, estimated grid voltage *e**β**,est *and estimation error and (c) actual AC-line currents.

Fig. 11. Transient performances of the PLL under symmetric grid voltages sag (experiment): (a) computed *dq *components (*ed*, *eq*) with actual grid voltages and computed *dq *components (*ed,est*, *eq,est*) with estimated grid voltages and (b) computed angles *θ *and *θ**est *with actual and estimated grid voltages, respectively.

Fig. 12. Transient performances of the AN estimator under grid voltages unbalance (experiment): (a) actual grid voltage *e**α*, estimated grid voltage *e**α**,est *and estimation error and (b) actual grid voltage *e**β*, estimated grid voltage *e**β**,est *and estimation error and (c) actual AC-line currents.

Fig. 13. Transient performances of the PLL under grid voltages unbalance (experiment): computed *dq *components (*ed*, *eq*) with actual grid voltages and computed *dq *components (*ed,est*, *eq,est*) with estimated grid voltages and (b) computed angles *θ *and *θ**est *with actual and estimated grid voltages, respectively.

Fig. 14. Transient performances of the AN estimator under distorted grid voltages (simulation): (a) actual grid voltage *e**α *and estimated grid voltage *e**α**,est*, (b) actual grid voltage *e**β *and estimated grid voltage *e**β**,est *and (c) actual AC-line currents.

Fig. 15. Transient performances of the PLL under distorted grid voltages (simulation): computed *dq *components (*ed*, *eq*) with actual grid voltages and computed *dq *components (*ed,est*, *eq,est*) with estimated grid voltages and (b) computed angles *θ *and *θ**est *with actual and estimated grid voltages respectively.

**CONCLUSION **

In this work, another AN estimator for killing the lattice voltage sensors in VOC of three-stage PWM rectifier has been proposed. The built up AN estimator joins estimation ability of the ANN and sifting property of the ANF. Lyapunov’s hypothesis based soundness investigation has been misused for ideal tuning of the AN estimator. Thus, basic, exact and quick framework voltages estimation has been gotten. To keep away from current overshoot and to lessen the settling time at the startup, another startup procedure has been proposed to instate the VOC. The adequacy of the proposed technique has been tentatively illustrated. A correlation between the proposed AN estimator and the as of late created SOGI based estimator has been directed. This examination has unmistakably shown quicker union and better exactness of the proposed estimator. At long last, power of the AN estimator in regards to step change in DC-interface voltage reference, stack obstruction variety and non-perfect lattice voltages conditions (symmetrical hang, unbalance, bending) has been researched through reproduction and test tests. The acquired outcomes have exhibited superior exhibitions of the proposed AN estimator inside the examined working conditions.