Reduced carrier PWM scheme with unified logical expressions for reduced switch count multilevel inverters

ABSTRACT:

The significant reduction in switch count of symmetrical/asymmetrical reduced switch count multilevel inverters (RSCMLI) topologies has modified the operation of inverter such that the conventional carrier-based pulse width modulation (PWM) schemes such as level-shifted PWM and phase-shifted PWM can no more realise them. To control these RSC-MLI topologies, reduced carrier PWM schemes with modified switching logic gained more prominence. These schemes involve suitable logical expressions to realise the switching states of the inverter. However, these logical expressions vary with topological arrangement and number of levels. Moreover, these schemes produce high total harmonic distortion (THD) in line-voltages. Therefore, to improve the line-voltage THD and generalise the switching logic, a modified reduced carrier PWM scheme with unified logical expressions is presented here. The proposed PWM scheme is directly valid for any topology and can be easily scalable to any number of levels in the inverters. To validate the implementation of the proposed PWM to control any RSC-MLI, experimental studies of various asymmetrical RSC-MLI topologies with the proposed PWM scheme are carried out. Further, to verify the superiority of the proposed scheme in terms of THD, complexity, scalability, and computation burden, its performance is compared with carrier-based PWM schemes reported in the literature.

 

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM: Fig. 1 Seven-level single-phase configuration of RSC-MLI-based MLDCL

  

EXPECTED SIMULATION RESULTS:

 Fig. 2 Phase-voltage waveforms and their corresponding harmonic spectra (scale: X-axis: 4 ms/div and Y-axis: 50 V/div) (a) MLDCL, (b) SSPS, (c) Switched dc sources, (e) E-type, (f) MLDCL with conventional reduced carrier PWM

Fig. 3 Line-voltage waveforms and their corresponding harmonic spectra (scale: X-axis: 10 ms/div and Y-axis: 100 V/div) (a) MLDCL, (b) SSPS, (c) Switched dc sources, (d) Hybrid T-type, (e) E-type, (f) MLDCL with conventional reduced carrier PWM

Fig. 4 Line-current waveforms and their corresponding harmonic spectra (scale: X-axis: 10 ms/div and Y-axis: 2 A/div) (a) MLDCL, (b) SSPS, (c) Switched dc sources, (d) Hybrid T-type, (e) E-type, (f) MLDCL with conventional reduced carrier PWM

  

CONCLUSION:

To overcome the limitations of conventional reduced carrier PWM scheme, this paper presented a modified reduced carrier PWM scheme with unified logical expressions. The efficacy of the proposed switching logic is validated with experimental studies on various 13-level asymmetrical RSC-MLI topologies. Further, superior performance of the proposed scheme is verified by comparing its performance with conventional carrier PWM schemes. Topology-independent operation, simplified switching logic generalization to higher levels, less computation burden, and improved line-voltage THD performance of the proposed reduced carrier PWM scheme serves as a viable solution to overcome the demerits of conventional multicarrier, reduced carrier, and multireference PWM schemes.

 

REFERENCES:

  • Gupta, K.K., Ranjan, A., Bhatnagar, P., et al.: ‘Multilevel inverter topologies with reduced device count: a review’, IEEE Trans. Power Electron., 2016, 31, (1), pp. 135–151
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  • Sanjeevan, A.R., Kaarthik, R.S., Gopakumar, K., et al.: ‘Reduced commonmode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source’, IET Power Electron., 2016, 9, (3), pp. 519–528
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