Real-Time Implementation of a 31-Level Asymmetrical Cascaded Multilevel Inverter for Dynamic Loads


Among the renewable energy applications, the most popular inverters are cascaded multilevel inverters. Irrespective of numerous benefits these inverters face reliability issues due to the presence of more circuit components in the design. This has been a critical challenge for researchers in designing inverters with enhanced reliability by reducing the total harmonic distortion (THD). This paper proposes a 31-level asymmetric cascaded multilevel inverter for renewable energy applications. The proposed topology produces waveforms consisting of the staircase with a high number of output levels with lesser components with low THD. The investigations on the feasibility and performance of MLI under steady-state, transient, and dynamic load disturbances. The results are validated from a 1.6kW system which provides the proposed inverter.


  1. Multilevel inverter (MLI)
  2. total harmonic distraction (THD)
  3. staircase modulation technique



The proposed inverter is tested experimentally with resistive and inductive loads. The output waveforms obtained during the resistive load test clearly show that the phase angle between current and voltage is zero. And the inductive load testing results show that the current is lagging voltage. To test the robustness of the proposed scheme, a load disturbances test is conducted. It is observed that the proposed topology is well stabilized under load disturbances conditions. The presented topology provides seven-level and thirty-one level output voltage with only 6 and 10 switches respectively in asymmetrical conditions. Under simulation a THD value of 3.62% is obtained using SIMULINK. under experimental conditions the computed THD value is 3.7%. The ability of presented MLI topology has been veri_ed using both simulation and experimental setups and the results are demonstrated for both conditions. The suggested topology is appropriate for the integration of medium-voltage renewable energy and power quality improvement in DVR, DStatcom and FACTs.


[1] T. Porselvi and R. Muthu, “Comparison of cascaded H-Bridge, neutral point clamped and _ying capacitor multilevel inverters using multicarrier PWM,” in Proc. Annu. IEEE India Conf., Dec. 2011, pp. 1_4.

[2] M. A. Hosseinzadeh, M. Sarbanzadeh, E. Sarbanzadeh, M. Rivera, and R. Grégor, “Back-to-back modi_ed T-type half-bridge module for cascaded multi-level inverters with decreased number of components,” in Proc. IEEE Int. Conf. Electr. Syst. Aircraft, Railway, Ship Propuls. Road Vehicles Int. Transp. Electri_c. Conf. (ESARS-ITEC), Nov. 2018, pp. 1_6.

[3] J. Rodríguez, J.-S. Lai, and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724_738, Aug. 2002.

[4] Y. Suresh, J. Venkataramanaiah, A. K. Panda, C. Dhanamjayulu, and P. Venugopal, “Investigation on cascade multilevel inverter with symmetric, asymmetric, hybrid and multi-cell con_gurations,” Ain Shams Eng. J., vol. 8, no. 2, pp. 263_276, 2017.

[5] N. Prabaharan, A. H. Fathima, and K. Palanisamy, “New hybrid multilevel inverter topology with reduced switch count using carrier based pulse width modulation technique,” in Proc. IEEE Conf. Energy Convers. (CENCON), Oct. 2015, pp. 176_180.

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