An Optimized Three Phase Multilevel Inverter Topology with Separate Level and Phase Sequence Generation Part


This manuscript presents an optimized, 3-ϕ, multilevel (MLI) inverter topology. The proposed system is derived by cascading the level generation part with the phase sequence generation part. Further, it can be operated at any required level depending upon the configuration of the level generation part. Thus, for higher level operation extra components are required at the level generation part only. Therefore, number of components required for the proposed MLI is lower than the conventional 3-ϕ MLI topologies for higher level operation. Further, the level generation part is shared by the three phases equally. This eliminates the possibility of phase unbalance. The working principle and the operation of the proposed MLI are supported with the simulation and experimental validations. Further, the proposed optimized MLI is also compared with the conventional 3-ϕ MLIs to prove its advantage.


  1. 3-ϕ
  2. Multilevel inverter
  3. Common mode voltage
  4. New topology



Fig. 1. (a) Circuit schematic for the proposed m-level MLI. (b) Configuration of top/bottom BU.



Fig 2. Simulation results showing the (a) line to line voltages, (b) Output voltage of top BU, (c) output voltage of bottom BU, (d) phase to neutral voltages and (e) load current waveforms of the proposed 3-ϕ MLI in symmetrical operation.


This paper presents an optimized 3-ϕ MLI configuration with reduced number of component. The prominent features of the proposed MLI are as follows.

1) The proposed MLI configuration is built by cascading LGP and PSGP.

2) For higher level operation only switches required are at the BUs only which resides in the LGP. This reduces the requirement of extra devices compared to conventional topologies.

3) Also, each dc voltage source in the presented MLI topology is equally shared by all the phases. Thus, any chance of inter-phase asymmetry is avoided.

The abovementioned points support that the proposed MLI is an optimized configuration for 3-ϕ operation with reduced number of switches. However, the proposed configuration is operated by using the SVs up-to the red line only. The further work with an improved PWM strategy which takes all the SVs in account, will be presented in the regular paper. This will further increase the number of levels at the output and linearity can be maintained in over-modulation region with improved dc-bus utilization.


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