In this paper, the details of the implementation of a multilevel dc-link inverter (MLDCLI), suitable for standalone application is presented. The first stage of the MLDCLI is a multilevel dc-link to provide a stepped dc voltage waveform approximating the shape of a rectified sine wave. This rectified sine wave is then inverted after every alternate cycle by a conventional single phase full bridge inverter. MLDCLI requires lesser number of switches thus reducing the number of gate drive circuits and switching complexities as compared to the conventional multilevel inverters (MLI). Hence MLDCLI is chosen for this work. The simulation of nine level cascaded half bridge MLDCLI in closed loop is carried out and results are presented. The hardware implementation of the MLDCLI in square wave staircase operation mode and in-phase level shifted multicarrier sine triangular pulse width modulation mode (IPD-SPWM) is carried out and results are presented. DSP TMS320F28069 is used for the implementation of MLDCLI.
- Cascaded half bridge MLDCLI
- PI compensator
Fig. 1 Generalized block diagram of MLDCLI
EXPECTED SIMULATION RESULTS:
Fig. 2. Simulation waveforms for closed loop system with kp=19.163 and
ki=22552 (a) Entire waveform (b) Enlarged view
Fig. 3. Harmonic profile of load voltage
Fig. 4. Simulation waveforms for closed loop system
The advantages of a nine level cascaded half bridge MLDCLI is studied, verified by a detailed simulation study and validated experimentally. The substantial reduction in number of components and associated advantages as compared to the conventional MLI makes cascaded half bridge MLDCLI a good choice for high power, medium voltage applications. The closed loop simulation results proved the tracking efficiency of the PI compensator. Square wave and IPDSPWM are the switching schemes selected for the implementation. It is verified from the results of the experimental prototype, that square wave switching scheme requires lower switching frequency and produces lower EMI than IPD-SPWM, but IPD-SPWM scheme has lower voltage THD. The experimental results of a scaled down laboratory prototype of a nine level cascaded half bridge MLDCLI using DSP TMS320F28069 is presented in this paper. The results obtained are in congruence with the theoretical claims and the simulation study.
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