Diode-clamped and cascaded H-bridge multilevel inverters are two of the main multilevel inverter topologies; each has its distinct advantages and drawbacks. Regarding the latter, cascaded H-bridge inverters require multiple separate dc sources, whereas (semi-active) diode-clamped inverters contain capacitors that require a means to balance their voltages. This paper investigates a hybrid-topology inverter, comprising a single-phase five-level semi-active diode-clamped inverter and a single-phase cascaded H-bridge inverter with their outputs connected in series, as one way to mitigate the drawbacks of each topology. The proposed control scheme for this inverter operates the switches at fundamental frequency to achieve capacitor voltage-balancing while keeping the switching losses low. Moreover, the step-angles are designed for the 13-level and 11-level output voltage waveform cases (as examples) for a fixed modulation index to achieve optimal total harmonic distortion. Furthermore, the scheme also achieves capacitor voltage-balancing for modulation indices that are close to the optimal modulation index, and for a wide range of load power factors, albeit at the cost of increased output voltage distortion. Simulation results are presented to help explain the processes of capacitor recharging and voltage-balancing, while experimental results are shown as verification of the expected behaviour of this inverter and the proposed control scheme.
Fig. 1. Five-level 1ϕ-DCMLI with semi-active front end
EXPECTED SIMULATION RESULTS:
Fig. 2 Simulated 13-level hybrid inverter output Vload (with waveform alternating between RM and DM cycle patterns), and capacitor voltages vc1, vc2, vc3 and vc4
Fig. 3. Simulated 13-level hybrid inverter output Vload (with waveform always in DM cycle pattern), and capacitor voltages vc1, vc2, vc3 and vc4
Fig. 4. Normalised harmonic spectra of the Vload waveforms obtained for the ideal, simulated and measured cases For RM operation, (b) For DM operation
Fig. 5: Simulation and test results for the 13-level hybrid inverter with various load PFs (a) 0 PF leading, (b) 0.1 PF lagging, (c) 0.95 PF leading
Fig. 6: Simulation and test results for the 13-level hybrid inverter with 0.95 lagging PF load (a) Simulated transition from RM to DM, and back to RM, (b) Measured transition from RM to DM, and back to RM
This paper has described the operation of a hybrid inverter comprised of a five-level 1ϕ-DCMLI with a semi-active front end connected in series with either a nine-level 1ϕ-CHBMLI or a seven-level 1ϕ-CHBMLI to produce a staircase waveform with either 13-levels or 11-levels, respectively. The key contribution is a novel fundamental-frequency modulation scheme for the DCMLI’s switches so as to charge up its inner dc-link capacitors from the CHBMLI’s dc sources, and thereby achieve capacitor voltage balancing via an alternation between a RM and a DM based on capacitor voltage feedback with a hysteresis band. Both simulation and experimental results have been presented herein to substantiate this hybrid-topology inverter’s good performance when operated using the proposed modulation and feedback control schemes at an optimal modulation index with unity PF loads. Furthermore, the scheme also achieves capacitor voltage balancing for modulation indices that span at least 10% above and below the optimal modulation index, and for a wide range of load PFs, albeit at the cost of increased output voltage distortion. While (fundamental-frequency) staircase modulation of the DCMLI has the advantage of lower switching losses and higher power efficiency compared with (high-frequency) pulse-width modulation, the accompanying drawback is it requires large capacitances to prevent overcharging, and also too-rapid discharging, of the capacitors due to the long charging and discharging durations. Future work will consider pulse-width modulation of the hybrid inverter, especially for variable instead of fixed modulation index applications, and for supplying lagging PF loads.
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