Design and Implementation of Seventeen LevelInverter With Reduced Components

 

ABSTRACT:

The multilevel inverters (MLI) are resourceful in producing a voltage waveform with superior-quality staircase counterfeit sinusoidal and depressed harmonic distortion (THD). Several conventional topologies are proposed to realize the MLI however, the limitations of these topologies may involve more DC sources and power-switching devices, and less THD, which in turn, increases the cost and size of the inverter. These drawbacks can be eliminated with the proposed hybrid Cascaded H-Bridge Multilevel Inverter with reduced components topology. As compared with the established MLI topologies the recommended topology having a reduced number of DC sources, power-switching devices, component count level factor, lesser TSV, more efficient, lesser THD, and cost-effective. The proposed MLI is a blend of a single-phase T-Type inverter and an H-Bridge module made of sub switches. This article incorporates the design and simulation of the multilevel inverter with staircase PWM technique. Further, the 9-level and 17-level MLI is examined with different combinational loads. The proposed inverter is stable during nonlinear loads, and it is well suited for FACTS and renewable energy grid-connected applications. An operational guideline has been explained with correct Figures and tables. The Output voltage wave is realized in numerical simulation. Finally, the experimental demonstrations were performed by implementing a hardware prototype setup for both linear and nonlinear loads using the dSPACE controller laboratory.

KEYWORDS:

  1. Hybrid cascaded H-bridge multilevel inverter with reduced components
  2. Pulse width modulation (PWM)
  3. Total harmonics distortion (THD)

SOFTWARE: MATLAB/SIMULINK

CONCLUSION:

In this article, a hybrid Cascaded H-Bridge Multilevel Inverter with reduced components topology was presented. The proposed basic MLI builds a voltage with nine levels and extended to seventeen levels by cascading. This topology uses lesser power switches that reduce the price and volume of the inverter and improves efficiency. The proposed inverter requires relatively less power electronic components to generate the desired output than other similar topologies. Comparative analysis shows that the proposed topology has a superior cost factor per level. In the output, the proposed inverter’s harmonic content is comparatively less than similar Cascaded H-Bridge MLI for both linear and nonlinear loads with nearly more efficiency _. The proposed inverter is stable during nonlinear loads, and it is well suited for FACTS and renewable energy grid-connected applications. To authenticate the proposed inverter satisfactory simulation is done in MATLAB/Simulink. The experimental setup is assembled in the laboratory confirmations unique with more significant output voltage levels, having lower harmonic content and reduced power switches, and greater efficiency. Subsequently proposed inverter appears some encouraging properties when compared with various similar topologies.

REFERENCES:

[1] P. Omer, J. Kumar, and B. S. Surjan, “A review on reduced switch count multilevel inverter topologies,” IEEE Access, vol. 8, pp. 22281_22302, 2020.

[2] C. Dhanamjayulu, S. R. Khasim, S. Padmanaban, G. Arunkumar, J. B. Holm-Nielsen, and F. Blaabjerg, “Design and implementation of multilevel inverters for fuel cell energy conversion system,” IEEE Access, vol. 8, pp. 183690_183707, 2020, doi: 10.1109/ACCESS.2020.3029153.

[3] C. Dhanamjayulu and S. Meikandasivam, “Implementation and comparison of symmetric and asymmetric multilevel inverters for dynamic loads,” IEEE Access, vol. 6, pp. 738_746, 2018.

[4] C. Dhanamjayulu and S. Meikandasivam, “Performance veri_cation of symmetric hybridized cascaded multilevel inverter with reduced number of switches,” in Proc. Innov. Power Adv. Comput. Technol. (i-PACT), Vellore, India, Apr. 2017, pp. 1_5.

[5] M. D. Siddique, S. Mekhilef, N. M. Shah, A. Sarwar, A. Iqbal, and M. A. Memon, “A new multilevel inverter topology with reduce switch count,” IEEE Access, vol. 7, pp. 58584_58594, 2019.

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