A Modified Three-Phase Four-Wire UPQC Topology With Reduced DC-Link Voltage Rating

 

ABSTRACT

The unified power quality conditioner (UPQC) is a custom power device, which mitigates voltage and current-related PQ issues in the power distribution systems. In this paper, a UPQC topology for applications with non-stiff source is proposed. The proposed topology enables UPQC to have a reduced dc-link voltage without compromising its compensation capability. This proposed topology also helps to match the dc-link voltage requirement of the shunt and series active filters of the UPQC. The topology uses a capacitor in series with the interfacing inductor of the shunt active filter, and the system neutral is connected to the negative terminal of the dc-link voltage to avoid the requirement of the fourth leg in the voltage source inverter (VSI) of the shunt active filter. The average switching frequency of the switches in the VSI also reduces, consequently the switching losses in the inverters reduce. Detailed design aspects of the series capacitor and VSI parameters have been discussed in the paper. A simulation study of the proposed topology has been carried out using PSCAD simulator, and the results are presented. Experimental studies are carried out on three-phase UPQC prototype to verify the proposed topology.

KEYWORDS

  1. Average switching frequency
  2. Dc-link voltage
  3. Hybrid topology
  4. Non-stiff source
  5. Unified power quality conditioner (UPQC)

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Equivalent circuit of proposed VSI topology for UPQC compensated system (modified topology).

 EXPECTED SIMULATION RESULTS

   

Fig. 2. Simulation results before compensation (a) load currents (b) terminal voltages.

Fig. 3. Simulation results using conventional topology. (a) DC capacitor voltages (top and bottom). (b) Source currents after compensation. (c) Voltage across the interfacing inductor in phase-a of the shunt active filter. (d) Shunt active filter currents. (e) Terminal voltages with sag, DVR-injected voltages, and load voltages after compensation.

   

Fig. 4. Simulation results with modified topology. (a) Voltage across series capacitor and load voltage in phase-a. (b) Inverter output voltage in leg-a of shunt active filter. (c) DC and fundamental values of voltage across series capacitor and inverter output voltage.

Fig. 5. Simulation results using modified topology. (a) DC capacitor voltages. (b) Source currents after compensation. (c) Voltage across the interfacing inductor in phase-a of the shunt active filter. (d) Shunt active filter currents. (e) Terminal voltages with sag, DVR injected voltages, and load voltages after compensation.

     CONCLUSION

A modified UPQC topology for three-phase four-wire system has been proposed in this paper, which has the capability to compensate the load at a lower dc-link voltage under nonstiff source. Design of the filter parameters for the series and shunt active filters is explained in detail. The proposed method is validated through simulation and experimental studies in a three-phase distribution system with neutral-clamped UPQC topology (conventional). The proposed modified topology gives the advantages of both the conventional neutral-clamped topology and the four-leg topology. Detailed comparative studies are made for the conventional and modified topologies. From the study, it is found that the modified topology has less average switching frequency, less THDs in the source currents, and load voltages with reduced dc-link voltage as compared to the conventional UPQC topology.

REFERENCES

[1] M. Bollen, Understanding Power Quality Problems: Voltage Sags and Interruptions. New York: IEEE Press, 1999.

[2] S. V. R. Kumar and S. S. Nagaraju, “Simulation of DSTATCOM and DVR in power systems,” ARPN J. Eng. Appl. Sci., vol. 2, no. 3, pp. 7–13, Jun. 2007.

[3] B. T. Ooi, J. C. Salmon, J. W. Dixon, and A. B. Kulkarni, “A three phase controlled-current PWM converter with leading power factor,” IEEE Trans. Ind. Appl., vol. IA-23, no. 1, pp. 78–84, Jan. 1987.

[4] Y. Ye, M. Kazerani, and V. Quintana, “Modeling, control and implementation of three-phase PWM converters,” IEEE Trans. Power Electron., vol. 18, no. 3, pp. 857–864, May 2003.

[5] R. Gupta, A. Ghosh, and A. Joshi, “Multiband hysteresis modulation and switching characterization for sliding-mode-controlled cascaded multilevel inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2344–2353, Jul. 2010.

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