New Approach for Harmonic Mitigation in Single Phase Five-Level CHBMI with Fundamental Frequency Switching

ABSTRACT:

The main objective of this paper is to study and analyse the voltage output waveform of a multilevel inverter, to suggest a new approach for harmonic mitigation improving the converter performance. These last type of converters represent a new technology in the field of DC/AC electrical energy conversion, presenting advantages respect to the traditional converters. In fact, the multilevel power converters present a low harmonic content and a high voltage level. The paper considers a five-level single-phase cascaded H-bridge inverter and fundamental frequency modulation techniques. The voltage waveform analysis has allowed to identify a working area of the converter where there are lowest values of the considered harmonic amplitude. The simulated behaviour of the model of the converter, with the logic piloting gate signals, has been obtained  in Matlab-Simulink environment.

 KEYWORDS:

  1. Multilevel Power Converter
  2. Soft switching
  3. Phase Shifted Voltage Cancellation

 SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

Fig. 1. Single-phase five-level CHBMI

EXPECTED SIMULATION RESULTS:

 

Fig. 2. Gate signals H-Bridge I with a=~=30°.

Fig. 3. Gate Signals H-Bridge 2 with a=~=30°.

Fig. 4. Voltage trend over time with a=~=30°.

CONCLUSION:

In this paper a fundamental switching modulation strategy for single-phase five-level CHBMI that mitigate low order harmonics is presented. The proposed method, through the control of the a and P parameters, allows the mitigation of third, fifth, seventh, ninth and eleventh harmonics. The values of the control parameters can be obtained without needs to solve a set of nonlinear transcendental equations. However, the fundamental harmonic amplitude can only be varied from 42% to 92% of 2 (Voc*4Yrr.

REFERENCES:

[I] K. Sivakumar, A. Das, R. Ramchand, C. Patel, and K. Gopakumar, A five-level inverter scheme for a four-pole induction motor drive by feeding the identical voltage-profile windings from both sides, IEEE Trans. Ind. Electron., vol. 57, no. 8,pp. 2776-2784, Aug. 2010.

[2] M. Caruso et a!., Design and experimental characterization of a low-cost, real-time, wireless AC monitoring system based on ATmega 328P-PU microcontroller, 2015 AEIT International Annual Conference (AEIT), Naples, 2015, pp. 1-6. doi: 1O.1109/AEIT.2015.7415267

[3] M. Caruso, R. Miceli, P. Romano, G. Schettino, C. Spataro and F. Viola, A low-cost, real-time monitoring system for PV plants based on ATmega 328P-PU microcontroller, 2015 IEEE International Telecommunications Energy Conference (INTELEC), Osaka, 2015, pp. 1-5. doi: 10.1109/INTLEC2015.7572270

[4] M. Caruso, V. Cecconi, A. O. Di Tommaso, and R. Rocha. A Rotor Flux and Speed Observer for Sensorless Single-Phase Induction Motor Applications. International Journal of Rotating Machinery, vol. 2012, no. 276906, p. 13,2012.

[5] M. Caruso, A O. Di Tommaso, F. Genduso, R. Miceli and G. R. Galluzzo, A DSP-Based Resolver-To-Digital Converter for High-Performance Electrical Drive Applications, in IEEE Transactions on Industrial Electronics, vol. 63, no. 7, pp. 4042- 4051, July 2016.

An Optimized Three Phase Multilevel Inverter Topology with Separate Level and Phase Sequence Generation Part

ABSTRACT:

This manuscript presents an optimized, 3-ϕ, multilevel (MLI) inverter topology. The proposed system is derived by cascading the level generation part with the phase sequence generation part. Further, it can be operated at any required level depending upon the configuration of the level generation part. Thus, for higher level operation extra components are required at the level generation part only. Therefore, number of components required for the proposed MLI is lower than the conventional 3-ϕ MLI topologies for higher level operation. Further, the level generation part is shared by the three phases equally. This eliminates the possibility of phase unbalance. The working principle and the operation of the proposed MLI are supported with the simulation and experimental validations. Further, the proposed optimized MLI is also compared with the conventional 3-ϕ MLIs to prove its advantage.

 KEYWORDS:

  1. 3-ϕ
  2. Multilevel inverter
  3. Common mode voltage
  4. New topology

 SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. (a) Circuit schematic for the proposed m-level MLI. (b) Configuration of top/bottom BU.

EXPECTED SIMULATION RESULTS:

 

Fig 2. Simulation results showing the (a) line to line voltages, (b) Output voltage of top BU, (c) output voltage of bottom BU, (d) phase to neutral voltages and (e) load current waveforms of the proposed 3-ϕ MLI in symmetrical operation.

CONCLUSION:

This paper presents an optimized 3-ϕ MLI configuration with reduced number of component. The prominent features of the proposed MLI are as follows.

1) The proposed MLI configuration is built by cascading LGP and PSGP.

2) For higher level operation only switches required are at the BUs only which resides in the LGP. This reduces the requirement of extra devices compared to conventional topologies.

3) Also, each dc voltage source in the presented MLI topology is equally shared by all the phases. Thus, any chance of inter-phase asymmetry is avoided.

The abovementioned points support that the proposed MLI is an optimized configuration for 3-ϕ operation with reduced number of switches. However, the proposed configuration is operated by using the SVs up-to the red line only. The further work with an improved PWM strategy which takes all the SVs in account, will be presented in the regular paper. This will further increase the number of levels at the output and linearity can be maintained in over-modulation region with improved dc-bus utilization.

REFERENCES:

[1] J. Rodriguez, J. Lai and F. Z. Peng, “Multilevel inverters: a survey of topologies, controls, and applications,” IEEE Trans. Ind. Elect., vol. 49, no. 4, pp. 724-738, Aug. 2002.

[2] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu and S. Jain, “Multilevel Inverter Topologies With Reduced Device Count: A Review,” IEEE Trans. Power Elect., vol. 31, no. 1, pp. 135-151, Jan. 2016.

[3] Wu, Bin, and Mehdi Narimani. High-power converters and AC drives. John Wiley & Sons, 2016.

[4] S. S. Fazel, S. Bernet, D. Krug and K. Jalili, “Design and Comparison of 4-kV Neutral-Point-Clamped, Flying-Capacitor, and Series-Connected H-Bridge Multilevel Converters,” IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. 1032-1040, July-aug. 2007.

[5] L. Wang, D. Zhang, Y. Wang, B. Wu and H. S. Athab, “Power and Voltage Balance Control of a Novel Three-Phase Solid-State Transformer Using Multilevel Cascaded H-Bridge Inverters for Microgrid Applications,” in IEEE Trans. Power Elect., vol. 31, no. 4, pp. 3289-3301, April 2016.

 

Implementation of Multilevel DC-Link Inverter for Standalone Application

 

ABSTRACT:

In this paper, the details of the implementation of a multilevel dc-link inverter (MLDCLI), suitable for standalone application is presented. The first stage of the MLDCLI is a multilevel dc-link to provide a stepped dc voltage waveform approximating the shape of a rectified sine wave. This rectified sine wave is then inverted after every alternate cycle by a conventional single phase full bridge inverter. MLDCLI requires lesser number of switches thus reducing the number of gate drive circuits and switching complexities as compared to the conventional multilevel inverters (MLI). Hence MLDCLI is chosen for this work. The simulation of nine level cascaded half bridge MLDCLI in closed loop is carried out and results are presented. The hardware implementation of the MLDCLI in square wave staircase operation mode and in-phase level shifted multicarrier sine triangular pulse width modulation mode (IPD-SPWM) is carried out and results are presented. DSP TMS320F28069 is used for the implementation of MLDCLI.

KEYWORDS:

  1. MLI
  2. MLDCLI
  3. Cascaded half bridge MLDCLI
  4. DSP
  5. PI compensator

 

SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM:

 Fig. 1 Generalized block diagram of MLDCLI

 EXPECTED SIMULATION RESULTS:

 Fig. 2. Simulation waveforms for closed loop system with kp=19.163 and

ki=22552 (a) Entire waveform (b) Enlarged view

Fig. 3. Harmonic profile of load voltage

Fig. 4. Simulation waveforms for closed loop system

CONCLUSION:

The advantages of a nine level cascaded half bridge MLDCLI is studied, verified by a detailed simulation study and validated experimentally. The substantial reduction in number of components and associated advantages as compared to the conventional MLI makes cascaded half bridge MLDCLI a good choice for high power, medium voltage applications. The closed loop simulation results proved the tracking efficiency of the PI compensator. Square wave and IPDSPWM are the switching schemes selected for the implementation. It is verified from the results of the experimental prototype, that square wave switching scheme requires lower switching frequency and produces lower EMI than IPD-SPWM, but IPD-SPWM scheme has lower voltage THD. The experimental results of a scaled down laboratory prototype of a nine level cascaded half bridge MLDCLI using DSP TMS320F28069 is presented in this paper. The results obtained are in congruence with the theoretical claims and the simulation study.

REFERENCES:

[1] Samir Kouro, Mariusz Malinowski, K. Gopakumar, Josep Pou, Leopoldo G. Franquelo, Bin Wu, Marcelo A. Pérez, “Recent Advances and Industrial Applications of Multilevel Converters,” IEEE Transactions On Industrial Electronics, vol. 57, no. 8, pp. 2553- 2577, Aug. 2010.

[2] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilvel converters arrives,” IEEE Ind.Electron. Mag., vol. 2, no. 2, pp. 28–39, Jun. 2008.

[3] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel converters: An enabling technology for high-power applications,” Proc. IEEE, vol. 97, no. 11, pp. 1786–1817, Nov. 2009.

[4] Gui-Jia Su, “Multilevel DC-Link Inverter”, IEEE Transactions On Industry Applications, vol. 41, no. 3, pp.848 – 854, May/June 2005.

[5] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, “Medium voltage multilevel converters—State of the art, challenges, and requirements in industrial applications,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2581– 2596, Aug. 2010.

A Single-Phase Cascaded Multilevel Inverter Composed of Four-Level Sub-multilevel Cells

ABSTRACT

This paper presents a novel cascaded multilevel inverter topology. The series connection of proposed basic cells is the main core of this topology. Different methods to determine the values of DC voltage sources in cells are investigated. Advantages and disadvantages of this topology in comparison with classical topologies are discussed. Symmetric and asymmetric structures of this topology are well analyzed through simulations.

 KEYWORDS

  1. Cascaded multilevel inverter
  2. Single phase

 SOFTWARE: MATLAB/SIMULINK

 GENERAL SCHEMATIC CIRCUIT DIAGRAM:

Fig.. 1. General scheme of proposed cascaded multilevel inverter

EXPECTED SIMULATION RESULTS


Fig. 2. Simulation results of two-cell proposed inverter Symmetric design: (a) va (b) Vaal and iout(c) THD Asymmetric design: (d) va (e) Vout and iout(f) THD

Fig.3.The blocking voltage of  switches(a) S11 and S12 (b)S21 and  S22  (c)S31 and S32 (d)S41 and S42 (e) Sa (f) Sb  (g) T1 and T4 (h)  T2 and T3.

 CONCLUSION

In this paper a new structure for multilevel inverters based on series connection of four-level sub-multilevel basic cells is proposed. The H-bridge inverter and additional circuit have been added to the basic form of the proposed inverter in order to generate positive and negative polarities and facilitate the symmetric and asymmetric implementations regarding the values of the dc sources. Different methods are suggested to choose the values of the dc sources and they are appraised by comparison studies with classical cascaded H-bridge inverter. The results of this survey illustrate the fact that the number of switches and the total blocking voltage of the inverter are reduced for the proposed topology compared to the classical ones. Finally, the simulation results on a two-cell inverter with symmetric and asymmetric implementation confirm the proper performance of the proposed topology.

 REFERENCES

[I] 1. Franquelo, J. Rodriguez, J. Leon, S. Kouro, R. Portillo, and M. EPrlaectst,ro “nT. hMea ga.g, e of multilevel converters arrives,” IEEE Ind. vol. 2, no. 2, pp. 28-39, Jun. 2008.

[2] J. Rodriguez, S. Member, J. Lai, and S. Member, “Multilevel Inverters : A Survey of Topologies , Controls , and Applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738,2002.

[3] J. Rodriguez, 1. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications,” Proc. IEEE, vol. 97, no. II, pp. 1786-1817, Nov. 2009.

[4] J.-S. 1. J.-S. Lai and F. Z. P. F. Z. Peng, “Multilevel converters-a new breed of power converters,” lAS ’95. Coif. Rec. 1995 IEEE Ind. Appl. Can! Thirtieth lAS Annu. Meet., vol. 3, no. 3, pp. 509-517,1995.

[5] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, E”Ale cStruorvne.,y on Cascaded Multilevel Inverters,” IEEE Trans. Ind. vol. 57, no. 7, pp. 2197-2206, Jul. 2010.

 

A Novel 7-Level Cascaded Inverter for Series Active Power Filter

ABSTRACT:

Harmonic voltage compensation of the load connected to the point of common coupling (PCC) by using a series of active power filter (SAPF) based on a single phase cascaded multilevel inverter is proposed. The proposed multilevel inverter are presented in detail. The inverter has the ability of acting as a harmonic source when the reference is a non-sinusoidal signal. To achieve this, a simple control technique is performed with the proposed inverter. A prototype of 7-level inverter based SAPF is manufactured without using a parallel passive filter (PPF) because it is designed to show SAPF own compensation capacity alone. Filtering ability of the SAPF is shown both in simulation and experimental studies. The validity of the proposed inverter based SAPF is verified by simulation as well as experimental study. The results show that the proposed multi-level inverter is suitable for SAPF applications.

KEYWORDS:

  1. Active power filter
  2. Multilevel inverter
  3. Harmonic compensation
  4. Half-bridge cascaded
  5. Power quality

 SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. The scheme of the proposed system.

EXPECTED SIMULATION RESULTS:

 

 (a) Simulation result (50 V/div), (5 ms/div)

Fig. 2. The waveform of VPCC before compensation

(a) Simulation result (50 V/div), (5 ms/div)

Fig. 3. The waveforms of the load voltage and the proposed inverter voltage after compensation.

 CONCLUSION:

This paper proposes a single phase cascaded inverter based SAPF. The 7-level inverter topology and operation principle is introduced. With the proposed topology, the number of output levels can easily be increased. Switching signals of the semiconductor devices used in the inverter are also obtained by a simple method. A SAPF with the proposed inverter topology is simulated.The aim of the simulation is to compensate the load voltage harmonics connected to PCC. In addition to the simulation, the proposed SAPF prototype is designed. Using this prototype, experimental study is performed. Simulation and experimental results similar each other proves the accuracy of the analysis. The load waveform that is highly distorted with a THD value of 24.12% is compensated with the proposed inverter based SAPF and the THD value is reduced to 3.80% in experimental study. This shows that the proposed inverter is suitable for SAPF applications.

REFERENCES:

[1] M. I. M. Montero, E. R. Cadaval, F. B. Gonzalez, “Comparison of control strategies for shunt active power filters in three-phase four-wire systems”, IEEE Trans. Power Electron., vol. 22, no. 1, pp. 229–236, 2007.

[2] F. Z. Peng, H. Akagi, and A. Nabae, “A new approach to harmonic compensation in power systems—A combined system of shunt passive and series active filters,” IEEE Trans. Ind. Appl., vol. 26, no. 6, pp. 983– 990, Nov./Dec. 1990.

[3] Z. Wang, Q. Wang, W. Yao, and J. Liu, “A series active power filter adopting hybrid control approach,” IEEE Trans. Power Electron., vol. 16, no. 3, pp. 301–310, May 2001.

[4] H. Akagi, “Trends in active power line conditioners,” IEEE Trans. Power Electron., vol. 9, no. 3, pp. 263–268, May 1994.

[5] M. El-Habrouk, M. K. Darwish, and P. Mehta, “Active power filters: A review,” IEE Electr. Power Appl., vol. 147, no. 5, pp. 403–413, Sep. 2000.

A New Six-Switch Five-Level Active Neutral Point Clamped Inverter for PV Applications

ABSTRACT:

Multilevel inverters are one of the preferred solutions for medium-voltage and high-power applications and have found successful industrial applications. Five-level Active Neutral Point Clamped inverter (5L-ANPC) is one of the most popular topologies among five-level inverters. A Six-Switch 5L-ANPC (6S-5L-ANPC) topology is proposed. Compared to the conventional 5L-ANPC inverters, the 6S-5L-ANPC reduces two active switches and has lower conduction loss. The proposed modulation enables the 6S-5L-ANPC inverter to operate under both active and reactive power conditions. The FC capacitance is designed under both active and reactive power conditions. The analysis shows the proposed topology is suitable for photovoltaic (PV) grid-connected applications. A 1KVA single-phase experimental prototype is built to verify the validity and flexibility of the proposed topology and modulation method.

KEYWORDS:

  1. Multilevel inverter
  2. Active Neutral Point Clamped (ANPC)
  3. Flying-Capacitor (FC)
  4. PWM modulation

SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

 

Fig.1. Configuration of the proposed 6S-5L-ANPC inverter.

EXPECTED SIMULATION RESULTS

 

Fig. 2. Simulation results with 310 uF FC value under unity power factor condition. (a) Inverter output voltage. (b) FC voltage. (c) Grid voltage and inverter output current. (d) THD of output current.

 

Fig. 3. Simulation results with 310 uF FC value under reactive power operation (PF = 0.9). (a) Inverter output voltage. (b) FC voltage. (c) Grid voltage and inverter output current. (d) THD of output current.

Fig. 4. Simulation results with 56 uF FC value under unity power factor condition. (a) Inverter output voltage. (b) FC voltage. (c) Grid voltage and inverter output current. (d) THD of output current.

Fig. 5. Simulation results with 56 uF FC value under reactive power operation (PF = 0.9). (a) Inverter output voltage. (b) FC voltage. (c) Grid voltage and inverter output current. (d) THD of output current.

Fig. 6. Simulation results under low switching frequency operation (PF = 1). (a) Inverter output voltage. (b) FC voltage. (c) Grid voltage and inverter output current.

Fig. 7. Simulation results under low switching frequency operation (PF = 0.9). (a) Inverter output voltage. (b) FC voltage. (c) Grid voltage and inverter output current.

Fig. 8. Simulation results with 15% FC voltage drop using different FC value.

CONCLUSION:

In this paper, a novel 6S-5L-ANPC inverter topology has been proposed. As compared with the conventional 5L-ANPC inverter, it requires only 6 switches for single phase, a reduction from 8 switches. The operating principles and switching states are presented. The results of comparison between 6S-5L-ANPC and the conventional 5L-ANPC topologies show that 6S-5L-ANPC topology has lower conduction loss and thus higher efficiency in high power condition. The specific modulation strategy of 6S-5L-ANPC inverter under reactive power operation has been proposed. Issues related to the DC-link capacitors and FC voltages balancing and the maximum reactive power capability are discussed. The equations to calculate the FC capacitance value in active and reactive power conditions are provided. Computer simulation and experimental prototype based on a single phase 1KVA prototype have been carried out in both active and reactive power conditions to demonstrate the reliability of the proposed topology and modulation method.

REFERENCES:

[1] F. Z. Peng, W. Qian, and D. Cao, “Recent advances in multilevel converter / inverter topologies and applications,” in Proc. IPEC, 2010, pp. 492–501.

[2] J. Rodriguez, Jih-Sheng Lai, and Fang Zheng Peng, “Multilevel inverters: a survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Apr. 2002.

[3] A. Sanchez-ruiz, M. Mazuela, S. Alvarez, G. Abad, and I. Baraia, “Medium voltage–high power converter topologies comparison procedure, for a 6.6 kV drive application using 4.5 kV IGBT modules,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1462–1476, Mar. 2012.

[4] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. W. Bin Wu, J. Rodriguez, M. a. Pérez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[5] J. Rodríguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilevel converters arrives,” IEEE Ind. Electron. Mag., vol. 2, no. 2, pp. 28–39, Jun. 2008.

A Multilevel Inverter Structure based on Combination of Switched-Capacitors and DC Sources

ABSTRACT:

This paper presents a switched-capacitor multilevel inverter (SCMLI) combined with multiple asymmetric DC sources. The main advantage of proposed inverter with similar cascaded MLIs is reducing the number of isolated DC sources and replacing them with capacitors. A self-balanced asymmetrical charging pattern is introduced in order to boost the voltage and create more voltage levels. Number of circuit components such as active switches, diodes, capacitors, drivers and DC sources reduces in proposed structure. This multi-stage hybrid MLI increases the total voltage of used DC sources by multiple charging of the capacitors stage by stage. A bipolar output voltage can be inherently achieved in this structure without using single phase H-bridge inverter which was used in traditional SCMLIs to generate negative voltage levels. This eliminates requirements of high voltage rating elements to achieve negative voltage levels. A 55-level step-up output voltage (27 positive levels, a zero level and 27 negative levels) are achieved by a 3-stage system which uses only 3 asymmetrical DC sources (with amplitude of 1Vin, 2Vin and 3Vin) and 7 capacitors (self-balanced as multiples of 1Vin). MATLAB/SIMULINK simulation results and experimental tests are given to validate the performance of proposed circuit.

KEYWORDS:

  1. Multi-level inverter
  2. Switched-capacitor
  3. Bipolar converter
  4. Asymmetrical
  5. Self-balancing

 SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig (1) Three stage structure of the proposed inverter

EXPECTED SIMULATION RESULTS

 

 Fig (2) Waveform of the output voltage in (a) 50Hz and pure resistive load (b the inset graphs of voltage and current

Fig (3) waveform of the output voltage in 50Hz with resistive-inductive load

Fig (4) Capacitor’s voltage in 50Hz (a) middle stage (b) last stage

CONCLUSION:

In this paper, a multilevel inverter based on combination of multiple DC sources and switched-capacitors is presented. Unlike traditional converters which used H-bridge cell to produce negative voltage that the switches should withstand maximum output AC voltage, the suggested structure has the ability of generating bipolar voltage (positive, zero and negative), inherently. Operating principle of the proposed SCMLI in charging and discharging is carried out. Also, evaluation of reliability has been done and because of high number of redundancy, there has been many alternative switching states which help the proposed structure operate correctly even in fault conditions. For confirming the superiority than others, a comprehensive comparison in case of number of devices and efficiency is carried out and shows that the proposed topology has better performance than others. For validating the performance, simulation and experimental results are brought under introduced offline PWM control method.

REFERENCES:

[1] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilevel converters arrives,” IEEE Trans. Ind. Electron. Mag., vol. 2, no. 2, pp. 28–39, June, 2008.

[2] M. Saeedifard, P. M. Barbosa and P. K. Steimer,”Operation and Control of a Hybrid seven Level Converter,” IEEE Trans. Power Electron., vol. 27, no.2, pp. 652–660, February, 2012.

[3] A. Nami. “A New Multilevel Converter Configuration for High Power High Quality Application,” PhD Thesis, Queensland University of Technology, 2010.

[4] V. Dargahi, A. K. Sadigh, M. Abarzadeh, S. Eskandari and K. Corzine, “A new family of modular multilevel converter based on modified flying capacitor multicell converters IEEE Trans. Power Electron., vol. 30, no.

1, pp. 138-147, January, 2015.

[5] I. López, S. Ceballos, J. Pou, J. Zaragoza, J. Andreu, I. Kortabarria and V. G. Agelidis,” Modulation strategy for multiphase Neutral-Point Clamped converters,” IEEE Trans. Power Electron., vol. 31, no. 2, pp. 928–941, March, 2015.

Novel Family of Single-Stage Buck-Boost Inverters Based on Unfolding Circuit

ABSTRACT:

This paper describes a novel family of single-phase single-stage buck-boost inverters using output unfolding circuits. Operation principles, component design guidelines along with modulation techniques are presented and discussed. The simulation results confirm all theoretical statements. Experimental setup of the most promising solution is assembled and tested, where the efficiency for different operation modes is analyzed. Finally, the pros and cons along with applications of the proposed solutions are discussed in the conclusions.

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. Family of the single-phase single-stage buck-boost inverters with unfolding circuits: single-inductor unfolding buck-boost inverter (a), tappedinductor unfolding buck-boost inverter (b), single-inductor twisted unfolding buck-boost inverter (c).

EXPECTED SIMULATION RESULTS:

Fig. 2..Simulation results of proposed circuits for boost case: the output voltage and the inductor`s current ((a) for circuit in Fig. 2a, (d) for circuit in Fig. 2b, (g) for circuit in Fig. 2c); the input voltage and the input current ((b) for circuit in Fig. 2a, (e) for circuit in Fig. 2b, (h) for circuit in Fig. 2c ); ripples of the output voltage and of the inductor`s current ((c) for circuit in Fig. 2a, (f) for circuit in Fig. 2b, (e) for circuit in Fig. 2c).

Fig. 3. Simulation results of proposed circuits for buck case: the output voltage and the inductor`s current ((a) for circuit in Fig. 2a, (d) for circuit in Fig. 2b, (g) for circuit in Fig. 2c); the input voltage and the input current ((b) for circuit in Fig. 2a, (e) for circuit in Fig. 2b, (h) for circuit in Fig. 2c); ripples of the output voltage and of the inductor`s current ((c) for circuit in Fig. 2a, (f) for circuit in Fig. 2b, (e) for circuit in Fig. 2c.

  

CONCLUSION:

This paper has presented a novel family of buck-boost inverters using output unfolding circuit. Component design guidelines along with modulation techniques are given. Simulation and experimental results confirmed the theoretical analysis. It is demonstrated that the main advantage of these solutions is the reduced size of passive elements in a wide range of input voltage regulation. It is achieved due to the direct dc to ac energy conversion without any dc-link stage. Despite the increased amount of semiconductors, the overall efficiency can be very high because only two semiconductors are involved in high switching performance in any period of operation. The solutions proposed can be recommended for PV applications where high power corresponds to high voltage. In advance, it gives reduced EMI compared to any other competitive solutions. At the same time, a continuous input current is achieved. The proposed modifications of the buck-boost inverters provide high selection flexibility. The buck-boost inverter with a tap-inductor and output unfolding circuit may provide very high step-up solutions. Another valuable advantage is the common voltage shape, which contains no high switching frequency components. As a result, leakage current problem does not exist for PV application.

 

REFERENCES:

  • Bortis, D. Neumayr, J. W. Kolar, “ηρ-Pareto optimization and comparative evaluation of inverter concepts considered for the GOOGLE Little Box Challenge”, in Proc. of IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1–5.
  • Ghosh; Miao-xin Wang; S. Mudiyula; U. Mhaskar; R. Mitova, D. Reilly; D. Klikic, “Industrial Approach to Design a 2-kVa Inverter for Google Little Box Challenge”, IEEE Trans. Ind. Electron., vol. 65, no. 7, pp. 5539-5549, July 2018.
  • Morsy, P. Enjeti, “Comparison of Active Power Decoupling Methods for High-Power-Density Single-Phase Inverters Using Wide- Bandgap FETs for GoogleLittle Box Challenge”, in IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 4, N 3, 2016, pp. 790–798.
  • Kaminski, O. Hilt, “SiC and GaN Devices – Competition or Coexistence,” in Proc. of Integrated Power Electronics Systems (CIPS), 7th International Conference on, 2012, pp. 1-11.
  • Chub, M. Zdanowski, A. Blinov, J. Rabkowski “Evaluation of GaN HEMTs for high-voltage stage of isolated DC-DC converters” in proc. of 10th International Conference on Compatibility.

A Seven-Switch Five-Level Active-Neutral-Point-Clamped Converter and Its Optimal Modulation Strategy

ABSTRACT:

Multilevel inverters are receiving more attentions nowadays as one of preferred solutions for medium and high power applications. As one of the most popular hybrid multilevel inverter topologies, the Five-Level Active-Neutral-Point-Clamped inverter (5L-ANPC) combines the features of the conventional Flying-Capacitor (FC) type and Neutral-Point-Clamped (NPC) type inverter and was commercially used for industrial applications. In order to further decrease the number of active switches, this paper proposes a Seven-Switch 5L-ANPC (7S-5L-ANPC) topology, which employs only seven active switches and two discrete diodes. The analysis has shown a lower current rating can be selected for the seventh switch under high power factor condition, which is verified by simulation results. The modulation strategy for 7S-5L-ANPC inverter is discussed. A 1KVA single-phase experimental prototype is built to verify the validity and flexibility of the proposed topology and modulation method.

KEYWORDS:

  1. Multilevel inverter
  2. Active-Neutral-Point-Clamped (ANPC) inverter
  3. Flying-Capacitor
  4. Pulse-Width-Modulation (PWM)

 SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

 

Fig.1 (a) Proposed topology.

 EXPECTED SIMULATION RESULTS

 

 Fig. 2. Simulation results under unity power factor condition. (a) Output voltage and FC voltage. (b) T7 current in case 1. (c) T7 current in case 2. (d) T7 current in case 3. (e) T7 current in case 4.

Fig. 3. Simulation results under reactive power condition (PF = 0.9, capacitive). (a) Output voltage and FC voltage. (b) T7 current in case 1. (c) T7 current in case 2. (d) T7 current in case 3. (e) T7 current in case 4

Fig. 4. Simulation results under reactive power condition (PF = 0). (a) Output voltage and FC voltage. (b) T7 current in case 1. (c) T7 current in case 2. (d) T7 current in case 3. (e) T7 current in case 4.

Fig. 5. Experimental results under unity power factor condition: waveforms of inverter output voltage, grid voltage, FC voltage and output current.

CONCLUSION:

In this paper, a novel 7S-5L-ANPC inverter topology has been proposed. As compared with the conventional 5L-ANPC inverter, it requires seven active switches for single phase and a low current rating switch can be selected for the seventh switch under high power factor situation. The operating principles and switching states are presented. The detailed comparison between the proposed topology and the conventional 5L-ANPC topologies in terms of voltage stress and efficiency is made. The specific modulation strategy of 7S-5L-ANPC inverter under reactive power operation has been proposed. Computer simulation and experimental prototype based on a single phase 1KVA prototype have been carried out in unity power factor condition and reactive power condition. The validity and advantages of the proposed topology and modulation method are demonstrated.

REFERENCES:

[1] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. W. Bin Wu, J. Rodriguez, M. a. Pérez, and J. I. Leon, “Recent advances and industrial applications of multilevel converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2553–2580, Aug. 2010.

[2] F. Z. Peng, W. Qian, and D. Cao, “Recent advances in multilevel converter / inverter topologies and applications,” in Proc. IPEC, 2010, pp. 492–501.

[3] F. Z. Peng, “A generalized multilevel inverter topology with self voltage balancing,” IEEE Trans. Ind. Electron., vol. 37, no. 2, pp. 611–618, Feb. 2001.

[4] J. Rodriguez, Jih-Sheng Lai, and Fang Zheng Peng, “Multilevel inverters: a survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724–738, Apr. 2002.

[5] L. M. Tolbert, “A Multilevel Modular Capacitor Clamped DC-DC Converter,” in Proc. 41st IAS, 2006, pp. 966–973.

An Improved H8 Topology for Common-mode Voltage Reduction

ABSTRACT:

This paper presents an improved H8 power converter for common-mode voltage reduction and electromagnetic interference suppression. The proposed H8 converter can realize zero common-mode voltage variation when entering and leaving the zero state, which is mainly achieved by both the improvement of the structure and the control strategy. For the system structure, two switches are added on the DC bus to float the AC part of the three phase converter in the zero state. Besides, additional capacitors are used to realize controllable common-mode voltage. For the control strategy, a simple control strategy is proposed for the H8 converter. It can automatically adapt to the flowing orientation of the load current to realize synchronous switching of the power switches, which effectively eliminates the impact of the dead time. Through analysis, simulations and experiment, a comparison between the proposed H8 converter and the conventional H6 converter is performed. Results validates the effectiveness of the H8 topology.

 

KEYWORDS:

  1. H8 topology
  2. Common-mode voltage reduction
  3. Electromagnetic interference source suppression.

 SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

Fig. 1. The topology of the proposed H8 converter.

 

EXPECTED SIMULATION RESULTS:

(a) Waveform of CMV in a fundamental circle.

(b) Waveform of CMV in a carrier circle.

(c) Waveform of CMV distortion.

Fig. 2. Comparison of the CMV of the proposed topology and conventional H6 topology

(a) 0 pF.

(b) 500 pF.

(c) 2.2 nF.

Fig. 3. Comparison of the CMV of the H8 converter with different additional capacitor.

 

CONCLUSION:

To reduce the CMV of the two level three phase power converter, an improved H8 converter is proposed in this study. The H8 topology disconnects the power supply and the AC output circuit in the zero state, and zero CMV variation is achieved though applying connection capacitors and specific control strategies. The performance of the proposed H8 converter is evaluated through theoretical analysis, simulations and experiments. Compared with the conventional H6 three phase topology, the proposed H8 much reduces the CMV in the zero state, which would be advantageous for the CMV-sensitive applications such as motor and photovoltaic systems. The suppressed CMV also results in the reduction of the common-mode EMI for a three phase converter. Besides, the proposed H8 topology precedes the previous H8 works by realizing zero CMV variation when entering and leaving zero state. Future work will be dedicated to the CMV suppression for other topologies.

 

REFERENCES:

  • Podrzaj, G. Gabic and M. Podhraski, “Introduction of some design aspects for improved performance of the DC/AC induction motor converter,” in Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2014 37th International Convention on, May. 2014.
  • Lorenzani, G. Migliazza, F. Bianchini, and G. Buticchi, “Ground Leakage Current in PV Three-phase Current Source Inverter Topologies,” in Industrial Electronics Society, IECON 2017 – 43rd Annual Conference of the IEEE, Nov. 2017.
  • Alhasheem, T. Dragicevic, and F. Blaabjerg, “Evaluation of multi predictive controllers for a two-level three-phase stand-alone voltage source converter,” in Power Electronics Conference (SPEC), 2017 IEEE Southern, Dec. 2017.
  • H. Akagi, and S. Tamura, “A Passive EMI Filter for Eliminating Both Bearing Current and Ground Leakage Current From an Inverter-Driven Motor,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1459-1469, 2006.
  • Gubia, P. Sanchis, A. Ursua, J. Lopez, and L. Marroyo, “Ground currents in single-phase transformerless photovoltaic systems,” Prog. Photovolt.: Res. Appl., vol. 15, no. 7, pp. 629–650, May. 2007.