A Novel Power Factor Correction Technique/or a Boost Converter

 

ABSTRACT:

The paper evolves a mechanism for improving the input power factor of an AC-DC-DC conversion system. It involves the process of shaping the input current wave to phase align with the input supply through a process of error compensation. The methodology includes cohesive formulation to arrive at nearly unity power factor and enjoy the etiquettes of output voltage regulation. The theory assuages to subscribe the benefits for the entire range of operating loads. It eliminates the use of passive components and fortifies the principles of pulse width modulation (PWM) for realizing the change in duty cycle. The MA TLAB based simulation results arbitrate the viability of the proposed approach and exhibit its suitability for use in real world applications.

 KEYWORDS:

  1. Ac-dc converter
  2. Power factor
  3. THD
  4. Voltage regulation

 SOFTWARE: MATLAB/SIMULINK

 CIRCUIT DIAGRAM:

image001

Figure 1. Power Factor Correction Control of Boost Converter

 EXPECTED SIMULATION RESULTS:

 image002

 Figure 2. Steady State Input AC Voltage and Input AC Current Waveform

image003

Figure 3. Steady State Rectified DC Voltage and Rectified DC Current Waveform

image004

Figure 4. Steady State Regulated DC Output Voltage and Regulated DC Output Current Waveform

image005

Figure 5. Power Factor Measurement of the Proposed Power Factor Correction Boost Converter

image006

Figure 6. FFT Spectrum of the AC input current of Proposed Power Factor Correction Boost Converter

image007

Figure 7. Transient response of Input AC Voltage and Input AC Current Waveform

image008

Figure 8. Transient Response of Rectified DC Voltage and Rectified DC Current Waveform

image009

Figure 9. Transient Response of Regulated DC Output Voltage and Regulated DC Output Current Waveform

image010

Figure 10. Power Factor Measurement of the Proposed Power Factor Correction Boost Converter at transient condition

CONCLUSION:

A single stage power factor correction strategy has been proposed for full bridge diode rectifier fed boost converter to support a 400W, lA DC load. The suitability of boost converter for power factor correction has been illustrated by the elimination of input capacitor filter and low output ripple factor. The formulated control design has been effectively orchestrated to correct the power factor in addition providing good voltage regulation. The transient performance has been portrayed to up-heave the strength of the control structure with an adequate output regulation and effective harmonic elimination. The control plan has been nurtured to standardize the THD level of the system that prevents the adverse effects of harmonics being injected in the grid. The exclusion of additional passive components and interleaving configuration has been fostered to reduce the size thus making it more adaptive to low cost compact electronic applications with high standards .

 REFERENCES:

[1] M. Milanovic, F . Mihalic, K. Jezernik and U. Milutinovic,” Single phase unity power factor correction circuits with coupled inductance,” Power Electronics Specialists Conference, 1992, vol.2, pp. l077-1082.

[2] M. Orabi and T Ninomiya, “Novel nonlinear representation for two stage power-factor-correction converter instability,” IEEE International Symposium on Industrial Electronics, 2003, voU, pp- 270-274.

[3] Yu Hung, Dan Chen, Chun-Shih Huang and Fu-Sheng Tsai, “Pulse-skipping power factor correction control schemes for ACIDC power converters,” Fourth International Conference on Power Engineering, Energy and Electrical Drives (POWERENG), 2013, pp-I087-1092.

[4] Lu, D.D. -C, H.H.-C. lu, V. Pjevalica, “A Single-Stage AC/DC Converter With High Power Factor, Regulated Bus Voltage, and Output Voltage,” Power Electronics, IEEE Transactions on, vo1.23, issue. I, pp. 218-228, Jan. 2008.

[5] M. Narimani and G. Moschopoulos, “A New Single-Phase SingleStage Three-Level Power Factor Correction AC-DC Converter,” Power Electronics, IEEE Transactions on , vol.27, issue.6, pp. 2888- 2899, June. 2012.

PV BALANCERS: CONCEPT, ARCHITECTURES, AND REALIZATION

 

ABSTRACT:

This paper presents a new concept of module integrated converters called PV balancers for photovoltaic applications. The proposed concept enables independent maximum power point tracking (MPPT) for each module, and dramatically decreases the requirements for power converters. The power rating of a PV balancer is less than 20% of its counterparts, and the manufacturing cost is thus significantly reduced. In this paper, two architectures of PV balancers are proposed, analyzed, realized, and verified through simulation and experimental results. It is anticipated that the proposed approach will be a low-cost solution for future photovoltaic power systems.

 

SOFTWARE: MATLAB/SIMULINK

 

BLOCK DIAGRAM:

Architecture I of PV balancers

(a) Architecture I of PV balancers

Architecture II of PV balancers

(b) Architecture II of PV balancers

Figure 1. Two possible architectures of PV balancers

 

EXPECTED SIMULATION RESULTS:

Output voltages of PV balancers in Architecture I

Figure 2. Output voltages of PV balancers in Architecture I

Output voltages of PV balancers in Architecture II

Figure 3. Output voltages of PV balancers in Architecture II

 

CONCLUSION:

A new concept of module-integrated converters called PV balancers has been proposed and verified in this paper. The proposed concept enables independent maximum power point tracking (MPPT) for each module, and dramatically decreases the requirements for power converters. PV balancers may have a significant economic value for photovoltaic systems in the future. Future work will be focused on power converter optimization, dc bus voltage control, and developing a highly efficient inverter for PV balancers.

REFERENCES:

  1. Kjaer, J. Pedersen and F. Blaabjerg, “A review of single-phase grid-connected inverters for photovoltaic modules,” IEEE Trans. Ind. App., vol. 41, no. 5, pp. 1292-1306, Sept. 2005.
  2. Linares, R. Erickson, S. MacAlpine, and M. Brandemuehl, “Improved energy capture in series string photovoltaic via smart distributed power electronics,” APEC’09, pp. 904-905, 2009.
  3. “Power circuit design for solar magic sm3320,” Application Note AN-2124, National Semiconductor, 2011.
  4. Trubitsyn, B. Pierquet, A. Hayman, G. Gamache, C. Sullivan, and D. Perreault, “High-efficiency inverter for photovoltaic applications,” ECCE’10, pp. 2803-2810, Sept. 2010.
  5. Pierquet, and D. Perreault, “A single-phase photovoltaic inverter topology with a series-connected power buffer,” ECCE’10, pp. 2811- 2818, Sept. 2010.

Investigation of PV Balancer Architectures on Practical Solar Photo Voltaic System

 

ABSTRACT:

In this paper, a trending concept of module integrated converter called as photovoltaic (PV) balancers is presented and verified on a practical data of solar PV system. This concept enables the maximum power point tracking for each module, which historically reduces the requirements for traditional power converters and significant economic impact on overall configuration of solar PV systems. In order to demonstrate the performance of the two possible architectures of PV balancers validated on a practical photovoltaic system and compared with the traditional module integrated converter presented in the literature. Thus, the obtained simulation results with PV balancers are superior in terms of power loss, rating, efficiency, regulation, and voltage stress on switching device.

 

KEYWORDS:

  1. Photovoltaic
  2. Maximum Power Point Tracking
  3. Module Integrated Converters
  4. PV Balancer

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Architecture-I

Fig.1. Architecture-I

 Architecture-II

Fig.2. Architecture-II

EXPECTED SIMULATION RESULTS:

PV Curves for DSP-100M panel

Fig. 3. PV Curves for DSP-100M panel

PV panel output currents

Fig. 4. PV panel output currents

PV panel output voltages 

Fig. 5. PV panel output voltages

PV balancer output voltages for architecture-I

Fig. 6. PV balancer output voltages for architecture-I

PV balancers output currents for architecture-I

Fig. 7. PV balancers output currents for architecture-I

PV balancer output voltages for architecture-II

Fig. 8. PV balancer output voltages for architecture-II

 PV balancers output currents for architecture-II

Fig. 9. PV balancers output currents for architecture-II

 

CONCLUSION:

This paper investigated the new concept of MIC called PV balancer with two possible architectures and demonstrated on a practical three module PV panels of PV systems. The investigations shows that the PV balancer has better efficiency, lower power rating, desirable voltage transformation ratio, low DC bus loss and good regulation ability as compared to the other commercial MIC. Among the two possible architectures, architecture-II provides the maximum power point tracking and decreases the few electrical requirements for overall photovoltaic systems. The work will be extended to propose different architectures on practical water pumping photovoltaic system with converter optimization, DC bus voltage control and developing a hardware testing module.

 

REFERENCES:

  1. Román, R. Alonso, P. Ibañez, S. Elorduizapatarietxe, and D. Goitia, “Intelligent PV Module for Grid-Connected PV Systems,” IEEE Trans. Indust. Elect., vol. 53, no. 4, August 2006.
  2. Zhao, K. Yeates, and Y. Han, “Analysis of high efficiency DC/DC converter processing partial input/output power,” in Proc. IEEE Workshop Control Modeling Power Electron, pp. 1–8.
  3. Olalla, D. Clement, M. Rodriguez, and D. Maksimovic, “Architecturesand control of submodule integrated dc–dc converters for photovoltaic applications,” IEEE Trans. Power Electron., vol. 28, no. 6, pp. 2980–2997, June 2013.
  4. Kjaer, J. Pedersen, and F. Blaabjerg, “A review of single-phase grid connected inverters for photovoltaic modules,” IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1292–1306, September 2005.
  5. Trubitsyn, B. Pierquet, A. Hayman, G. Gamache, C. Sullivan, and D. Perreault, “High-efficiency inverter for photovoltaic applications,” in Proc. Energy Convers. Cong. Expo., pp. 2803–2810, September 2010.

LLC Resonant Inverter for Induction Heating with Asymmetrical Voltage-Cancellation Control

ABSTRACT

This paper proposes a high efficiency LLC resonant inverter for induction heating applications by using asymmetrical voltage cancellation control. The proposed control method is implemented in a full-bridge topology for induction heating application. The operating frequency is automatically adjusted to maintain a small constant lagging phase angle under load parameter variation. The output power is controlled using the asymmetrical voltage cancellation technique. The LLC resonant tank is designed without the use of output transformer. This results in an increase of the net efficiency of the induction heating system. The validity of the proposed method is verified through computer simulation and hardware experiment at the operating frequency of 93 to 96 kHz.

 

SOFTWARE: MATLAB/SIMULINK

 

BLOCK DIAGRAM:

Full-bridge series and parallel resonant inverter.

Fig. 1. Full-bridge series and parallel resonant inverter.

EXPECTED SIMULATION RESULTS

Voltage and current waveforms at 100 % duty cycle

Fig. 2. Voltage and current waveforms at 100 % duty cycle

Simulation results with α=70o

Fig. 3. Simulation results with α=70o

CONCLUSION

This work proposes the full-bridge LLC resonant inverter for induction heating application. The phase-locked loop allows resonant frequency tracking under load parameter variation. The analytical expression of the output power as a function of the shifted phase angle is given in this work. Based on the derived expression, the asymmetrical voltage cancellation can be used to control output power to the induction coil. Simulation and experimental studies are performed to verify the proposed control method. The resonant frequency tracking and the adjustment of pulse voltage together ensure the maximum power transfer to the load throughout the heating cycle with minimal loss.

 

REFERENCES

  1. Kamli, S. Yamamoto, and M. Abe, “A 50-150 kHz Half- Bridge Inverter for induction heating Application,” IEEE Trans. Industrial Electronics, Vol. 43, February 1996. pp. 163-172
  2. J. Davies , J. and Simpson, P., 1979, Induction Heating Handbook. , McGraw-Hill, UK ,
  3. Chudjuarjeen, S., Koompai, C.and Monyakul, “Full-bridge current-fed inverter with automatic frequency control for forging application”, IEEE Tencon 2004, Vol. 4, pp.128-131, Nov. 2004
  4. Viriya, P.; Sittichok, S.; Matsuse, K.; “Analysis of High-Frequency Induction Cooker with Variable Frequency Power Control,” Power Conversion Conference, 2002 .PCC Osaka 2002 .Proceedings of the Volume 3, 5 -2 April 2002Page(s): 1507 – 1502vol.. 3
  5. Nam-Ju Park, Dong-Yun Lee, and Dong-Seok Hyun,”A Power-Control Scheme With Constant Switching Frequency in Class-D Inverter for Induction-Heating Jar Application”, IEEE Trans. Industrial Electronics, vol. 54, no. 3, Jun. 2007

Doubly Fed Induction Generator for Wind Energy Conversion Systems with Integrated Active Filter Capabilities

ABSTRACT

This paper deals with the operation of doubly fed induction generator (DFIG) with an integrated active filter capabilities using grid-side converter (GSC). The main contribution of this work lies in the control of GSC for supplying harmonics in addition to its slip power transfer. The rotor-side converter (RSC) is used for attaining maximum power extraction and to supply required reactive power to DFIG. This wind energy conversion system (WECS) works as a static compensator (STATCOM) for supplying harmonics even when the wind turbine is in shutdown condition. Control algorithms of both GSC and RSC are presented in detail. The proposed DFIG-based WECS is simulated using MATLAB/Simulink. A prototype of the proposed DFIGbased WECS is developed using a digital signal processor (DSP). Simulated results are validated with test results of the developed DFIG for different practical conditions, such as variable wind speed and unbalanced/single phase loads.

 KEYWORDS

  1. Doubly fed induction generator (DFIG)
  2. Integrated active filter
  3. Nonlinear load
  4. Power quality
  5. Wind energy conversion system (WECS).

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

image001

Fig. 1. Proposed system configuration.

image002

Fig. 2. Control algorithm of the proposed WECS.

EXPECTED SIMULATION RESULTS

Simulated performance of the proposed DFIG-based WECS at fixed wind speed of 10.6 m/s (rotor speed of 1750 rpm).

Fig. 3. Simulated performance of the proposed DFIG-based WECS at fixed wind speed of 10.6 m/s (rotor speed of 1750 rpm).

Simulated waveform and harmonic spectra of (a) grid current (iga), (b) load current (ila), (c) stator current (isa), and (d) grid voltage for phase “a” (vga) at fixed wind speed of 10.6 m/s (rotor speed of 1750 rpm).

Fig. 4. Simulated waveform and harmonic spectra of (a) grid current (iga), (b) load current (ila), (c) stator current (isa), and (d) grid voltage for phase “a” (vga) at fixed wind speed of 10.6 m/s (rotor speed of 1750 rpm).

Simulated performance of the proposed DFIG-basedWECS working as a STATCOM at zero wind speed

Fig. 5. Simulated performance of the proposed DFIG-basedWECS working as a STATCOM at zero wind speed.

image006

Fig. 6. Simulated waveforms and harmonic spectra of (a) load current (ila) and (b) grid current (iga) working as a STATCOM at wind turbine shut down condition.

image007

Fig. 7. Simulated performance of proposed DFIG for fall in wind speed.

Dynamic performance of DFIG-based WECS for the sudden removal and application of local loads.

Fig. 8. Dynamic performance of DFIG-based WECS for the sudden removal and application of local loads.

CONCLUSION

The GSC control algorithm of the proposed DFIG has been modified for supplying the harmonics and reactive power of the local loads. In this proposed DFIG, the reactive power for the induction machine has been supplied from the RSC and the load reactive power has been supplied from the GSC. The decoupled control of both active and reactive powers has been achieved by RSC control. The proposed DFIG has also been verified at wind turbine stalling condition for compensating harmonics and reactive power of local loads. This proposed DFIG-based WECS with an integrated active filter has been simulated using MATLAB/Simulink environment, and the simulated results are verified with test results of the developed prototype of this WECS. Steady-state performance of the proposed DFIG has been demonstrated for a wind speed. Dynamic performance of this proposed GSC control algorithm has also been verified for the variation in the wind speeds and for local nonlinear load.

 REFERENCES

  1. M. Tagare, Electric Power Generation the Changing Dimensions. Piscataway, NJ, USA: IEEE Press, 2011.
  2. M. Joselin Herbert, S. Iniyan, and D. Amutha, “A review of technical issues on the development of wind farms,” Renew. Sustain. Energy Rev., vol. 32, pp. 619–641, 2014.
  3. Munteanu, A. I. Bratcu, N.-A. Cutululis, and E. Ceang, Optimal Control of Wind Energy Systems Towards a Global Approach. Berlin, Germany: Springer-Verlag, 2008.
  4. A. B. Mohd Zin, H. A. Mahmoud Pesaran, A. B. Khairuddin, L. Jahanshaloo, and O. Shariati, “An overview on doubly fed induction generators controls and contributions to wind based electricity generation,” Renew. Sustain. Energy Rev., vol. 27, pp. 692–708, Nov. 2013.
  5. S. Murthy, B. Singh, P. K. Goel, and S. K. Tiwari, “A comparative study of fixed speed and variable speed wind energy conversion systems feeding the grid,” in Proc. IEEE Conf. Power Electron. Drive Syst. (PEDS’07), Nov. 27–30, 2007, pp. 736–743.

Simulation of a Space Vector PWM Controller for a Three-Level Voltage-Fed Inverter Motor Drive

ABSTRACT

Multilevel voltage-fed inverters with space vector pulse width modulation strategy are gained importance in high power high performance industrial drive applications. This paper proposes a new simplified space vector PWM method for a three-level inverter fed induction motor drive. The three- level inverter has a large number of switching states compared to a two-level inverter. In the proposed scheme, three-level space vector PWM inverter is easily implemented as conventional two-level space vector PWM inverter. Therefore, the proposed method can also be applied to multilevel inverters. In this work, a three-level inverter using space vector modulation strategy has been modeled and simulated. Simulation results are presented for various operation conditions using R-L load and motor load to verify the system model.

 

KEYWORDS

  1. Space vector PWM
  2. Three-level inverters
  3. Multilevel inverters

 

SOFTWARE: MATLAB/SIMULINK

 BLOCK DIAGRAM:

image001

Fig.1 Three level multilevel inverter using cascaded inverters with separated DC sources

 

EXPECTED SIMULATION RESULTS

image002

Fig.2 The line output voltage waveform for fo=10Hz and m=0.65

image003

Fig.3 Three-phase line output current waveforms for fo=10Hz and m=0.65

image004

Fig.4 The line output voltage waveform and its spectrum for fo=10Hz and m=0.65.

image005

Fig.5 The line output voltage waveform for fo=50Hz and m=0.7

CONCLUSION

The space vector PWM algorithm for a three level voltage-fed inverter using cascaded H-bridges inverter has been modeled and simulated using Simulink/MATLAB package program. Simulation results have been given for both R-L and induction motor loads using 1 kHz switching frequency with various output frequencies. The proposed control algorithm used in the three-level inverter can be easily applied to multilevel inverters with more than three levels. It has been shown that high quality waveforms at the output of the multilevel inverter can be obtained even with 1 kHz of low switching frequency.

 

REFERENCES

  1. M. Bhagwat and V.R. Stefanovic, “Generalized Structure of A Multilevel Inverter”, IEEE Trans. On I.A., Vol. IA-19, n.6, 1983, pp. 1057-1069.
  2. K. Mondal, J.O.P Pinto, B.K. Bose, “A Neural- Network-Based Space Vector PWM Controller for a Three-Level Voltage-Fed Inverter Induction Motor Drive”, IEEE Trans. on I.A., Vol. 38, no. 3, May/June 2002, pp.660-669.
  3. K. Mondal, B.K. Bose, V. Oleschuk and J.O.P Pinto, “Space Vector Pulse Width Modulation of Three-Level Inverter Extending Operation Into Overmodulation Region”, IEEE Trans. on Power Electronics, Vol. 18, no. 2, March 2003, pp.604-611.
  4. Manjrekar and G. Venkataramanan, “Advanced Topologies and Modulation Strategies for Multilevel Inverters”, Power Electronics Specialists Conference, Vol. 2, 23-27 June 1996, pp. 1013-1018.
  5. Nabae, I. Takahashi and H. Akagi, “A New Neutral-Point-Clamped PWM Inverter”, IEEE Trans. on I.A., Vol. 17, No.5, September/October 1981, pp.518-523.

Performance Investigation of Space Vector Pulse Width Modulated Inverter fed Induction Motor Drive

ABSTRACT

This paper introduces Space Vector Pulse Width Modulation (SVPWM) Technique in detail and its implementation in MATLAB. Performance investigation of Sinusoidal Pulse Width Modulated and Space Vector Modulated Voltage Source Inverter (VSI) fed Induction Motor (1M) drive has done and their simulation results are compared with each other. Also FFT analysis for Sinusoidal Pulse Width Modulated and Space Vector Pulse Width Modulated VSl fed 1M drive is done and compared with each other. 20 HP 1M is used. The study confirms that 1M gives improved performance when it is fed from Space Vector Pulse Width Modulated VS1.

 

KEYWORDS

  1. Space Vector Pulse Width Modulation (SVPWM)
  2. Sinusoidal Pulse Width Modulation (SPWM)
  3. Two Level Voltage Source Inverter (VSI)
  4. Total Harmonic Distortion (THD)
  5. Three Phase Induction Motor (1M).

 

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

image001

Figure 1. Block diagram of SVPWM

EXPECTED SIMULATION RESULTS

image002

Figure 2. (a) Line to Line Voltage (Vab) of Space Vector Modulated VSI (b) Stator current (i,..) of IM (c) Electromagnetic Torque (Te) of IM (d) Rotor Speed (Nm) of 1M.

image003

Figure 3 (a) Line to Line Voltage (Vab) of Sinusoidal Pulse Width Modulated VSI (b) Stator current (i,a) of IM ( c) Electromagnetic Torque (Te) of IM (d) Rotor Speed (Nm) of IM

image004

Figure 4. FFT Analysis of Line to Line Voltage (Vab) of (a) Sinusoidal Pulse Width Modulated VSL (b) Space Vector Modulated VSL

CONCLUSION

The simulation study of SVPWM technique was presented and compared with SPWM technique. It was found that by using SVPWM technique, THD content present in inverter output voltage is less as compared with SPWM technique. Table III shows that the utilization of DC bus is l3.55% more for SVPWM compared TO SPWM technique. i. e. SVPWM technique achieved a better utilization of DC bus as compared with SPWM technique. The performance investigation of SPWM inverter and SVPWM inverter fed 1M drive was done. Table IV shows, in case of SVPWM increased rotor speed with reduced error band achieved as compared with SPWM. Also settling time is less for SVPWM as compared with SPWM. It was conclude that results for SVPWM technique are more convenient than SPWM technique.

 

REFERENCES

  1. W. Van der Broeck, H. C. Skudelny and G. V. Stanke, “Analysis and realization of a pulsewidth modulator based on voltage space vectors,” IEEE Trans. Ind. Applicat., vol. 24,no. I, pp. 142-150, Jan.lFeb. 1988.
  2. Fukuda, Y. Iwaji, and H. Hasegawa, “PWM technique for inverter with sinusoidal output current,” IEEE Trans. Power Electron., vol. 5, no. I, pp. 54-61, Jan. 1990.
  3. Kolar, H. Ertl, and F. C. Zach, “Inf1uence of the modulation method on the conduction and switching losses of a PWM converter system,” IEEE Trans. Ind. Application., vol. 27, no. 6, pp. 1063-1075, Nov.lDec. 1991.
  4. Joachim Holtz,. “Pulsewidth modulation – A survey,” IEEE Trans. on Ind. Electron, vol. 1, pp. 11-18, Dec. 1992.
  5. H. Kwon and B. D. Min, “A fully software-controlled PWM rectifier with current link,” IEEE Trans. Ind. Electron., vol. 40, no. 3, pp. 355-363, June 1993.

Control of Induction Motor Drive using Space Vector PWM

 ABSTRACT

In this paper speed of induction motor is controlled which is fed from three phase bridge inverter. In this paper the speed of an induction motor can be varied by varying input Voltage or frequency or both. Variable voltage and variable frequency for Adjustable Speed Drives (ASD) is invariably obtained from a three-phase Voltage Source Inverter (VSI). Voltage and frequency of inverter can be easily controlled by using PWM techniques, which is a very important aspect in the application of ASDs. A number of PWM techniques are there to obtain variable voltage and variable frequency supply such as PWM, SPWM, SVPWM to name a few, among the various modulation strategies SVPWM is one of the most efficient techniques as it has better performance and output voltage is similar to sinusoidal. In SVPWM the modulation index in linear region will also be high when compared to other.

KEYWORDS

  1. Adjustable Speed Drive (ASD)
  2. Voltage source inverter (VSI)
  3. Sinusoidal PWM (SPWM)
  4. Space Vector PWM (SVPWM)

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

image001

Figure 1. Three-phase voltage source PWM Inverter

EXPECTED SIMULATION RESULTS

image002

Figure 2. Inverter o/p line voltages

image003

Figure 3 Motor Speed and Electromagnetic torque

CONCLUSION

The simulation of “Control of Induction Motor Drive Using Space Vector PWM” is carried out in MATLAB/Simulink. The simulation has been done for open loop as well as closed control. The appropriate output results are obtained. The variation of speed of Induction Motor has been observed by varying the load torque in open loop control and results are noted down in the table. Also observed that for the change in input speed commands the motor speed is settled down to its final value within 0.1sec in closed loop model.

 REFERENCES

  1. Abdelfatah Kolli, Student Member, IEEE, Olivier Béthoux, Member, IEEE, Alexandre De Bernardinis, Member, IEEE, Eric Labouré, and Gérard Coquery “Space-Vector PWM Control Synthesis for an H-Bridge Drive in Electric Vehicles” IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 62, NO. 6, JULY 2013. pp. 2241-2252.
  2. Sandeep N Panchal, Mr. Vishal S Sheth, Mr. Akshay A Pandya “Simulation Analysis of SVPWM Inverter Fed Induction Motor Drives” International Journal of Emerging Trends in Electrical and Electronics (IJETEE) Vol. 2, Issue. 4, April-2013. pp. 18-22 .
  3. Haoran Shi, Wei Xu, Chenghua Fu and Yao Yang. “Research on Threephase Voltage Type PWM Rectifier System Based on SVPWM Control” Research Journal of Applied Sciences, Engineering and Technology 5(12): 3364-3371, 2013. pp. 3364-3371.
  4. Mounika, B. Kiran Babu, “Sinusoidal and Space Vector Pulse Width Modulation for Inverter” International Journal of Engineering Trends and Technology (IJETT) – Volume4Issue4- April 2013. pp.1012-1017.
  5. Vinoth Kumar, Prawin Angel Michael, Joseph P. John and Dr. S. Suresh Kumar. “Simulation and Comparison Of Spwm And Svpwm Control For Three Phase Inverter” ARPN Journal of Engineering and Applied SciencesVOL. 5, NO. 7, JULY 2010. pp. 61-74.

 

A New Cascaded Switched-Capacitor Multilevel Inverter Based on Improved Series-Parallel Conversion with Less Number of Components

ABSTRACT

The aim of this study is to present a new structure for switched-capacitor multilevel inverters (SCMLIs) which can generate a great number of voltage levels with optimum number of components for both symmetric and asymmetric value of dc voltage sources. Proposed topology consists of a new switched-capacitor dc/dc converter (SCC) which has boost ability and can charge capacitors as self-balancing by using proposed binary asymmetrical algorithm and series-parallel conversion of power supply. Proposed SCC unit is used in new configuration as a sub-multilevel inverter (SMLI) and then, these proposed SMLIs are cascaded together and create a new cascaded multilevel inverter topology which is able to increase the number of output voltage levels remarkably without using any full H-bridge cell and also can pass the reverse current for inductive loads. In this case, two half bridges modules besides two additional switches are employed in each of SMLI units instead of using a full H-bridge cell which contribute to reduce the number of involved components in the current path, value of blocked voltage, the variety of isolated dc voltage sources and as a result the overall cost by less number of switches in comparison with other presented topologies. The validity of the proposed SCMLI has been carried out by several simulation and experimental results.

KEYWORDS

  1. Cascade sub-multilevel inverter
  2. Series-parallel conversion
  3. Self-charge balancing
  4. Switched-capacitor

SOFTWARE: MATLAB/SIMULINK

CIRCUIT DIAGRAM:

image001

Fig. 1. Proposed 17-level structure

 EXPECTED SIMULATION RESULTS

   image002

  • (a)
  • image003
  • (b)

Fig. 2. Steady states output voltage and current waveforms (a) in simulation Fig. 12. Transient states of output waveforms in simulation (b) in experiment ( 250V/div& 2A/div)

image004

Fig. 3. Transient states of output waveforms in simulation

  • image005
  •                                                                                             (a)                                   (b)

Fig. 4. Harmonic orders (a) output voltage (b) output current in simulation

image006

Fig. 5. Observed output voltage waveform at no-load condition (250V/div)

   image007

image008

 (a)

image009

image010

 (b)

Fig. 6. Capacitors’ voltage ripple waveforms for first case study (a) in simulation (b) in experiment (25 V/dev&50V/div)

 image011

image012

 

 image013

image014

 

image015

    

Fig. 7. Blocked voltage waveforms across switches of S1 (25V/div), S2 (100V/div), T1 (50V/div), T2 and T3 (100V/div) from left to right in the experiment

image016

                                                                                          (a)

image017     (b)

Fig. 8. Output voltage and current waveforms for (a) inductive load in experiment (250 V/div & 2 A/div) (b) sudden step load in simulation

image018

image019

(a)

image020

image021

(b)

Fig. 9. Observed capacitors’ current (a) in simulation (b) in experiment (2A/div)

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Fig. 10. (a) laboratory prototype (b) Output 49-level voltage and current waveforms in the experiment (250V/div & 2A/div)

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Fig. 11. Across voltage waveforms of capacitors in upper and lower stages of SCCs in proposed 49-level inverter (a) v C 1 lower stage (5V/div) (b) v C 2 lower stage (10V/div) (c) v C 1 upper stage(25V/div) (d) v C 2 upper stage(50V/div)

 

CONCLUSION

In this paper, at the first, a new reduced components SCC topology was presented which has boost capability remarkably and also can pass the reverse current for inductive loads through existing power switches. The voltage of all capacitors in this structure is balanced by binary asymmetrical algorithm. Next, a new sub-multilevel structure based on suggested SCC was proposed which can generate all of the voltage levels at the output (even and odd). In this case, the conventional output H-bridge cell used to convert the polarity of SCC units, has been removed, therefore number of required IGBTs and other involved components, are decreased. After that, an optimizing  operation was presented which could obvious the number of required capacitors in each of SCC units that participate in the cascade sub-multilevel inverter (CSMLI) to generate maximum number of output voltage levels with less number of elements. Moreover comprehensive comparisons were given which prove the differences between improved symmetric and asymmetric CSMLIs in contrast to some of recently presented topologies in variety aspects. Finally, to confirm the performance and effectiveness of proposed CSMLI, several simulation and experimental results have been presented.

REFERENCES

[1] J. Chavarria, D. Biel, F. Guinjoan, C. Meza, and J. J. Negroni, “Energy balance control of PV cascaded multilevel grid-connected inverters under level-shifted and phase-shifted PWMs,” IEEE Trans. Ind. Electron. vol. 60, no. 1, pp. 98–111, Jan. 2013.

[2] G. Buticchi, E. Lorenzani, and G. Franceschini, “A five-level single-phase grid-connected converter for renewable distributed systems,” IEEE Trans. Ind. Electron., vol. 60, no. 3, pp. 906–918, Mar. 2013.

[3] J. Rodriguez, L. J.Sheng, and P. Fang Zheng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind Electron., vol. 49, no. 4, pp. 724–738, Aug. 2002.

[4] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, “The age of multilevel converters arrives,” IEEE Trans. Industrial Electronic Magazine, vol. 2, no. 2, pp. 28–39, Jun. 2008.

[5] M. M. Renge and H. M. Suryawanshi, “Five-Level Diode Clamped Inverter to Eliminate Common Mode Voltage and Reduce dv/dt in Medium Voltage Rating Induction Motor Drives,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1598-1607, Jul. 2008.

 

Fixed Switching Frequency Sliding Mode Control for Single-Phase Unipolar Inverters

ABSTRACT:
Sliding mode control (SMC) is recognized as robust controller with a high stability in a wide range of operating conditions, although it suffers from chattering problem. In addition, it cannot be directly applied to multi switches power converters. In this paper, a high performance and fixed switching frequency sliding mode controller is proposed for a single-phase unipolar inverter. The chattering problem of SMC is eliminated by smoothing the control law in a narrow boundary layer, and a pulse width modulator produces the fixed frequency switching law for the inverter. The smoothing procedure is based on limitation of pulse width modulator. Although the smoothed control law limits the performance of SMC, regulation and dynamic response of the inverter output voltage are in an acceptable superior range. The performance of the proposed controller is verified by both simulation and experiments on a prototype 6-kVA inverter. The experimental results show that the total harmonic distortion of the output voltage is less than 1.1% and 1.7% at maximum linear and nonlinear load, respectively. Furthermore, the output dynamic performance of the inverter strictly conforms the standard IEC62040-3. Moreover, the measured efficiency of the inverter in the worst condition is better than 95.5%.
KEYWORDS:
1. Pulse width modulator
2. Sliding mode control
3. Unipolar single phase inverter

SOFTWARE: MATLAB/SIMULINK

BLOCK DIAGRAM:

Fig. 1. Proposed controller for single-phase inverters with a resonator in voltage loop.

EXPECTED SIMULATION RESULTS:

Fig. 2. Simulation result. a) Output voltage and current at 6-kW linear load. b) Output voltage and current at 6-kVA nonlinear load with CF = 2.75 and PF = +0.7.

Fig. 3. Simulation result: transient response of the output voltage for linear step load from zero to 100%

Fig. 4. Simulation result: transient response of the output voltage for linear
step load from 100% to zero.

Fig. 5. Experimental result: efficiency of inverter versus output power.

CONCLUSION:
In this paper, a fixed frequency SMC was presented for a single-phase inverter. The performance of the proposed controller has been demonstrated by a 6-kVA prototype. Experimental results show that the inverter is categorized in class1 of the IEC64020-3 standard for output dynamic performance. The inverter efficiency was measured up to 95.5% in the worst case.

Since the direct SMC cannot be applied to four switches unipolar inverter and it also suffers from the chattering problem, a PWM is employed to generate a fixed frequency switching law. The PWM modulates the smoothed discontinuous control law which is produced by SMC. To smooth the control law, the limitation of the PWM was considered.

The simulation and experimental results show that the load regulation is about 1% at the steady state as well. But, to obtain better regulation, a resonance compensator was added in the voltage loop. With this compensator, the load regulation was measured which has been below 0.2%.

REFERENCES:
[1] G. Venkataramanan and D.M. Divan, “Discrete time integral sliding mode control for discrete pulse modulated converters,” in Proc. 21st Annu. IEEE Power Electron. Spec. Conf., San Antonio, TX, 1990, pp. 67–73.
[2] J.Y.Hung,W. Gao, and J. C.Hung, “Variable structure control:Asurvey,” IEEE Trans. Ind. Electron., vol. 40, no. 1, pp. 2–22, Feb. 1993.
[3] E. Fossas and A. Ras, “Second order sliding mode control of a buck converter,” in Proc. 41st IEEE Conf. Decision Control, 2002, pp. 346– 347.
[4] C. Rech, H. Pinheiro, H. A. Gr¨undling, H. L. Hey, and J. R. Pinheiro, “A modified discrete control law for UPS applications,” IEEE Trans. Power Electron., vol. 18, no. 5, pp. 1138–1145, Sep. 2003.
[5] K. S. Low, K. L. Zhou, and D.W.Wang, “Digital odd harmonic repetitive control of a single- phase PWM inverter,” in Proc. 30th Annu. Conf. IEEE Ind. Electron. Soc., Busan, Korea, Nov. 2–6, 2004, pp. 6–11.